Patents by Inventor Yves Rody

Yves Rody has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8370773
    Abstract: Method and apparatus for designing an integrated circuit by calculating an optimised reticle layout design from an IC layout design and a model describing an optical system for transferring the IC layout design onto a semiconductor wafer using a reticle, wherein the IC layout design comprises features defined by a plurality of boundaries. Approximating the plurality of boundaries to generate an approximated IC layout design suitable for the manufacture of the IC. Performing OPC simulation on at least a portion of the approximated IC layout design.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: February 5, 2013
    Assignees: Freescale Semiconductor, Inc., Koninklijke Philips Electronics N.V.
    Inventors: Kevin Dean Lucas, Robert Elliott Boone, Yves Rody
  • Publication number: 20100333048
    Abstract: Method and apparatus for designing an integrated circuit by calculating an optimised reticle layout design from an IC layout design and a model describing an optical system for transferring the IC layout design onto a semiconductor wafer using a reticle, wherein the IC layout design comprises features defined by a plurality of boundaries. Approximating the plurality of boundaries to generate an approximated IC layout design suitable for the manufacture of the IC. Performing OPC simulation on at least a portion of the approximated IC layout design.
    Type: Application
    Filed: August 16, 2006
    Publication date: December 30, 2010
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Kevin Dean Lucas, Robert Elliott Boone, Yves Rody
  • Patent number: 7615318
    Abstract: For cases where one edge of a design feature is to be printed through a shifter mask and another one is to be printed through a binary trim mask, and where no upsizing can be performed due to the local density of the design, it is proposed to add shifters with respect to the shifter mask in such a way that all the edges are printed by the phase shift mask.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: November 10, 2009
    Assignees: Freescale Semiconductor Inc., STMicroelectronics (Crolles 2) SAS
    Inventors: Kyle Patterson, Yves Rody, Christophe Couderc, Corinne Miramond-Collet
  • Publication number: 20080261375
    Abstract: A method for forming a semiconductor device includes identifying an area that comprises an active device region, wherein the area has a perimeter at a first location and at least a portion of the edge of the active device region is coincident with at least a portion of the perimeter, expanding the perimeter to a first distance away from the first location, wherein the first distance defines a first point of a dummy feature, determining a second point of the dummy feature, adding the dummy feature to a layout using the first point and the second point, and using the layout to form a layer in a semiconductor device.
    Type: Application
    Filed: December 14, 2005
    Publication date: October 23, 2008
    Applicant: Freescale Semiconductor, Inc.
    Inventors: Kevin Lucas, Robert Boone, Judith Mueller, Rainer Thoma, Yves Rody
  • Publication number: 20060188792
    Abstract: For cases where one edge of a design feature is to be printed through a shifter mask and another one is to be printed through a binary trim mask, and where no upsizing can be performed due to the local density of the design, it is proposed to add shifters with respect to the shifter mask in such a way that all the edges are printed by the phase shift mask.
    Type: Application
    Filed: October 18, 2005
    Publication date: August 24, 2006
    Applicants: Freescale Semiconductor Inc., STMicroelectronics (Crolles 2) SAS
    Inventors: Kyle Patterson, Yves Rody, Christophe Couderc, Corinne Miramond-Collet