Abstract: A method for reducing the number of bits in a binary word (AI) which represent a series of addresses, called initial addresses, having a first step (E1) which successively extracts from each initial address (AI) at least one bit (C1) with a fixed rank; forms (1) an address called the selection address (AS) from each bit or bits (C1); extracts from each initial address (AI) a series of bits (C3, C6) using a format (M1i) selected from multiple predetermined first formats (M11, M12, M13, M14), as a function of the selection address; forms (2) with this series of bits (C3, C6) a binary word called the first relative address (AV1); and adds this first relative address to an address called the predetermined basic address (AB(M1i)) associated with the format (M1i) selected to determine this first relative address so as to obtain an address called the first reduced address (AT1) having a smaller number of bits than the initial address (AI); and wherein the basic address (AB(M1 i)) associated with the one (M1i) in the

Abstract: A logical machine operating according to a predetermined state diagram for performing state transitions on information in telecommunication transmission frames, each of the transmission frames having a plurality of repeated concatenation information which is indicative of the structure of the transmission frames, each of the transmission frames also having data information and pointer information which is indicative of the location of the data information in the transmission frames, characterized in that the logical machine performs the state transitions in the predetermined state diagram as a simultaneous function of all the repeated concatenation information of the transmission frame.

Abstract: The application is for telecommunication networks of asynchronous transfer mode. The device contains a time stamp generator (TSG) for assigning a time stamp to each cell; a buffer memory (BM); an address memory (FSAM) for memorizing the address of the first sub-cell of each cell; a link memory (LM); and a circuit for indicating the address of the buffer memory that contains the first sub-cell of a cell.

Abstract: The device is for telecommunication networks with an asynchronous transfer mode and contains, in particular:a time stamp generator (TSG), for assigning a time stamp to each cell;a buffer memory (BM);an address memory (FSAM) to memorize the address of the first sub-cell of each cell;a linking memory (LM);a circuit (CU) for finding the buffer memory address containing the first sub-cell of a cell; this circuit comprises, in particular: a memory that is accessible by its content, for memorizing the waiting cell identifiers, each containing the identity of a time period during which the waiting delay of the cell expires, and of the identity of at least one output from which the cell is to be emitted; and a queuing memory for each output, where the order number is recorded each time the waiting delay of at least one cell, which must be emitted from that output, expires; each queuing memory is of the type accessible by its content, and the numbers are searched in ascending order when this output becomes available.