Abstract: A processor core is accessed. The core is configured to execute instructions associated with an instruction set architecture (ISA). The core comprises a plurality of compute slices, a plurality of barrier register files, and a control unit. Each compute slice includes at least one arithmetic logic unit (ALU), a local register file, and is coupled to a successor compute slice and a predecessor compute slice by a barrier register file. Code associated with the ISA is evaluated, where the code includes a first loop. The evaluating includes generating iteration transfer information associated with the first loop. Each slice task within a plurality of slice tasks associated with the first loop is distributed to a compute slice. The processor core executes the plurality of slice tasks. Data forwarding between successive compute slices is based on the plurality of barrier register files and the iteration transfer information.

Abstract: Techniques for checking memory operations are disclosed. A processing unit is accessed, comprising compute slices, control unit, local memory disambiguation units (LMDUs), and a global MDU (GMDU). Each slice includes an execution unit and is coupled to successor and predecessor slices. Each slice is coupled to an LMDU. Each LMDU is coupled to the GMDU. A first slice executes a first slice task. The task includes a load instruction and address. The slice issues the load to an LMDU, saving load information in a memory operation table (MOT). For a not fully serviced load instruction, the LMDU sends the load information to the GMDU, storing load information in a global MOT (GMOT). The GMOT detects address aliasing between the load address and a previously issued address saved in the GMOT. The GMOT forwards memory information from previously issued memory instructions to the MOT to satisfy the load instruction.

Abstract: Techniques for task processing within an array of compute elements are disclosed. A two-dimensional (2D) array of compute elements, a control unit, and a memory system are accessed. Each compute element is coupled to its neighboring compute elements and includes a plurality of shadow state registers. A set of directions is provided for compute element operation and memory access precedence. Execution of a compiled task is started. Execution of the compiled task is halted at a point in time. An architectural state is saved at the point of the halting into a shadow SRAM. A bit in the shadow state SRAM representing a portion of the architectural state of the 2D array is set. The architectural state of the 2D array that was altered within the shadow SRAM is restored. Execution of the compiled task is started in the architectural state that was altered.

Abstract: Techniques for task processing using a highly parallel processing architecture with a compiler are disclosed. A two-dimensional array of compute elements is accessed. Each compute element within the array of compute elements is known to a compiler and is coupled to its neighboring compute elements within the array of compute elements. A set of directions is provided to the hardware, through a control word generated by the compiler, for compute element operation and memory access precedence. The set of directions enables the hardware to properly sequence compute element results. The set of directions controls data movement for the array of compute elements. A compiled task is executed on the array of compute elements, based on the set of directions. The compute element results are generated in parallel in the array, and the compute element results are ordered independently from control word arrival at each compute element.

Abstract: Method and device for combining images from at least two light projectors, the images having a transition zone between them, wherein the dimensions of the transition zone is known, and the emitted light toward the transition zone from each projector is based on a predetermined transfer function from input signal to projected image for each projector in the transition zone, so as to obtain predictable image characteristics in the transition zone.