Patents by Inventor Øyvind Janbu

Øyvind Janbu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220329716
    Abstract: A method for determining one or more groups of exposure settings to use in a 3D image acquisition process carried out with an imaging system, the 3D image acquisition process comprising capturing one or more sets of image data on the image sensor using the respective groups of exposure settings, wherein the one or more sets of image data are such as to allow the generation of one or more 3D point clouds defining the three-dimensional coordinates of points on the surface(s) of one or more objects being imaged, each group of exposure settings specifying a value for one or more parameters of the imaging system, wherein the method comprises identifying one or more candidate groups of exposure settings and selecting from the candidate groups of exposure settings, one or more groups of exposure settings that satisfy one or more optimization criteria.
    Type: Application
    Filed: June 19, 2020
    Publication date: October 13, 2022
    Inventors: Øystein SKOTHEIM, Henrik SCHUMANN-OLSEN, Alexey STEPANOV, Øyvind JANBU, Martin INGVALDSEN, Jens T. THIELEMANN
  • Patent number: 10317508
    Abstract: A radio frequency (RF) device is provided. The RF device includes an antenna interface, a receive circuit configured to extract data from incoming signals, a playback circuit configured to associate a predefined delay with the data, a transmit circuit configured to generate outgoing signals based on the data and the predefined delay, and a control circuit configured to calculate range based in part on the predefined delay and phase differences between incoming signals and outgoing signals.
    Type: Grant
    Filed: January 6, 2014
    Date of Patent: June 11, 2019
    Assignee: SILICON LABORATORIES INC.
    Inventor: Øyvind Janbu
  • Patent number: 9240794
    Abstract: A phase-locked loop (PLL) is provided. The PLL may include a local oscillator configured to generate an output signal, a feedback divider configured to generate a feedback signal in response to the output signal, a phase detector configured to operate the local oscillator based on a comparison between a reference signal and the feedback signal, and a reset controller in communication with each of the phase detector and the feedback divider. The reset controller may be configured to hold each of the phase detector and the frequency divider in reset, and enable each of the phase detector and the frequency divider such that at least the feedback signal is in substantial synchronization with the reference signal.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: January 19, 2016
    Assignee: Silicon Laboratories, Inc
    Inventors: Pål Øyvind Reichelt, Øyvind Janbu
  • Patent number: 9240795
    Abstract: A system and method of calibrating a phase-locked loop (PLL) having at least a phase detector, a frequency divider and a local oscillator are provided. The disclosed example includes generating a lock window signal based on a feedback signal generated by the frequency divider where the lock window signal may form an active lock window relative to each significant edge of the feedback signal, generating a sampled window signal based on samples of the lock window signal at each significant edge of a reference signal, and estimating a phase offset between the reference signal and the feedback signal based on a number of consecutive samples of the sampled window signal that are active.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: January 19, 2016
    Assignee: Silicon Laboratories, Inc.
    Inventors: Pål Øyvind Reichelt, Øyvind Janbu
  • Publication number: 20150222275
    Abstract: A phase-locked loop (PLL) is provided. The PLL may include a local oscillator configured to generate an output signal, a feedback divider configured to generate a feedback signal in response to the output signal, a phase detector configured to operate the local oscillator based on a comparison between a reference signal and the feedback signal, and a reset controller in communication with each of the phase detector and the feedback divider. The reset controller may be configured to hold each of the phase detector and the frequency divider in reset, and enable each of the phase detector and the frequency divider such that at least the feedback signal is in substantial synchronization with the reference signal.
    Type: Application
    Filed: January 31, 2014
    Publication date: August 6, 2015
    Applicant: Silicon Laboratories, Inc.
    Inventors: Pål Øyvind Reichelt, Øyvind Janbu
  • Publication number: 20150222278
    Abstract: A system and method of calibrating a phase-locked loop (PLL) having at least a phase detector, a frequency divider and a local oscillator are provided. The disclosed example includes generating a lock window signal based on a feedback signal generated by the frequency divider where the lock window signal may form an active lock window relative to each significant edge of the feedback signal, generating a sampled window signal based on samples of the lock window signal at each significant edge of a reference signal, and estimating a phase offset between the reference signal and the feedback signal based on a number of consecutive samples of the sampled window signal that are active.
    Type: Application
    Filed: January 31, 2014
    Publication date: August 6, 2015
    Applicant: Silicon Laboratories, Inc.
    Inventors: Pål Øyvind Reichelt, Øyvind Janbu
  • Publication number: 20150195725
    Abstract: A radio frequency (RF) device is provided. The RF device includes an antenna interface, a receive circuit configured to extract data from incoming signals, a playback circuit configured to associate a predefined delay with the data, a transmit circuit configured to generate outgoing signals based on the data and the predefined delay, and a control circuit configured to calculate range based in part on the predefined delay and phase differences between incoming signals and outgoing signals.
    Type: Application
    Filed: January 6, 2014
    Publication date: July 9, 2015
    Applicant: Silicon Laboratories Inc.
    Inventor: Øyvind Janbu