Abstract: A method and medium for performing subroutine return operations. Test operations are performed in parallel with other operations in a return operation. These test operations and the return operations are performed in response to a single instruction.

Abstract: An apparatus for performing multiply-accumulate operations in a microprocessor comprising operand input registers for receiving data to be operated on an adder and a multiplier for performing operations on the data, a result output port for presenting results to the microprocessor, a multiplexer for storing results, an accumulator cache for storing an accumulator value internal to the apparatus, and control circuitry for controlling the operation of the apparatus.

Abstract: An apparatus and method for saving and operating on a register set, shadow register file, and memory is presented. A register within a register set that is associated with an active execution state in a computing system is used as an address pointer to a memory location. The content of the memory location is either loaded from memory into an identified shadow register, or the content of a shadow register is stored into the memory location. The operation is normally performed by executing a single instruction by a processor or by circuitry associated with a processor or computer system. Active and inactive execution states may be under the control of an operating system running on the processor or computer system.

Abstract: An apparatus for scaling numbers comprises register means for storing an operand to be scaled, bit shifting means for performing a right shift operation on the operand, rounding means, and decision means to test for the existence of at least one of an overflow and an underflow condition.

Abstract: A system and method for preserving power in a microprocessor pipeline. The system includes a register file read control unit, the read control unit being configured to monitor one or more outputs from a control/decode unit of the pipeline and monitor write addresses from one or more other stages of the pipeline. The system also includes one or more read inhibit units each having an input, an output, and an enable terminal, the output of each of the one or more read inhibit units being coupled to a unique register port of a register file within the pipeline. The input of each of the one or more read inhibit units being coupled to the control/decode unit, and the enable terminal of each of the one or more read inhibit units being coupled to a unique output of the read control unit.

Abstract: A microprocessor circuit useful for indexed addressing of byte-addressable memories includes word-length index, base address, and destination registers designated by an instruction. The instruction also specifies one byte packed within the index register, which is to be extracted. A multiplexer has a word-wide input end accessing all of the bytes of the index register, and responsive to byte selection control passes the specified byte to its output. The extracted byte is provided directly at specific bit positions of a zero-extended address offset word. The offset word is added to the base address, the sum being used to address memory contents that are loaded into the destination register.

Abstract: A combined native (RISC or CISC) microprocessor and stack (Java) machine are constructed so that Java VM instructions can be executed in hardware. Most Java instructions are executed directly, while more complex Java instructions, such as those manipulating Java objects, are executed as native microcode. In order for native microcode instructions to access the Java operand stack, a Java operand stack pointer points to the register file location that is the current top of the stack, while a remap bit in the status register indicates that registers specified in native instructions are remapped as the maximum Java operand stack pointer value minus the present value of the Java operand stack pointer.

Abstract: A microprocessor architecture for executing byte compiled Java programs directly in hardware. The microprocessor targets the lower end of the embedded systems domain and features two orthogonal programming models, a Java model and a RISC model. The entities share a common data path and operate independently, although not in parallel. The microprocessor includes a combined register file in which the Java module sees the elements in the register file as a circular operand stack and the RISC module sees the elements as a conventional register file. The integrated microprocessor architecture facilitates access to hardware-near instructions and provides powerful interrupt and instruction trapping capabilities.