Abstract: In an approach, a processor receives a plurality of first operand values, where the first operand values are integer values. A processor adds, using binary addition, the plurality of first operand values resulting in a sum value S. A processor determines a single combined modular correction term D for a binary sum of all operand values based on leading bits of the sum value S. A processor performs a modular addition of S and D resulting in a modular sum of said plurality of said first operand values.

Abstract: A cache purge simulation system includes a device under test with a cache skip switch. A first cache skip switch includes a configurable state register to indicate whether all of an associated cache is purged upon receipt of a cache purge instruction from a verification system or whether a physical partition that is smaller than the associated cache is purged upon receipt of the cache purge instruction from the verification system. A second cache skip switch includes a configurable start address register comprising a start address that indicates a beginning storage location of a physical partition of an associated cache and a configurable stop address register comprising a stop address that indicates a ending storage location of the physical partition of the associated cache.

Abstract: Generation of test data for verifying a modular correction of a modular multiplication performed by a multiplier unit for very wide operands includes performing, by a multiplier unit using a computer, a modular multiplication by correcting a binary multiplication of two operands by a coarse-grained and a fine-grained correction. The computer selects adjacent intervals of the intermediate result, defines a sub-interval closely around a boundary between the adjacent intervals, and selects a value in the sub-interval. Moreover, the computer uses a first factorization algorithm for the value V for determining operands A?, B?, where the modular multiplication result of the operands corrected by the coarse-grained correction is in the sub-interval. The computer repeatedly determines A? plus varying ?-values as A? values, and determines B? values, so that the modular multiplication corrected by the coarse-grained correction is in the sub-interval.

Abstract: A cache purge simulation system includes a device under test with a cache skip switch. A first cache skip switch includes a configurable state register to indicate whether all of an associated cache is purged upon receipt of a cache purge instruction from a verification system or whether a physical partition that is smaller than the associated cache is purged upon receipt of the cache purge instruction from the verification system. A second cache skip switch includes a configurable start address register comprising a start address that indicates a beginning storage location of a physical partition of an associated cache and a configurable stop address register comprising a stop address that indicates a ending storage location of the physical partition of the associated cache.