Abstract: A method of communication between a first circuit and a second circuit coupled together over a two-line bus having a clock line and a data line. A power signal is provided to the second circuit over the two-line bus by setting the clock line and the data line to different potential levels. A bit is transmitted from one of the first circuit and the second circuit to the other of the first circuit and the second circuit by setting the data line to a potential level according to a state of the bit to be transmitted when the clock line is set at a first potential level. A bit is read in response to a transition of the clock line from the first potential level to a second potential level, different from the first potential level.

Abstract: A method of communication between a first circuit and a second circuit coupled together over a two-line bus having a clock line and a data line. A power signal is provided to the second circuit over the two-line bus by setting the clock line and the data line to different potential levels. A bit is transmitted from one of the first circuit and the second circuit to the other of the first circuit and the second circuit by setting the data line to a potential level according to a state of the bit to be transmitted when the clock line is set at a first potential level. A bit is read in response to a transition of the clock line from the first potential level to a second potential level, different from the first potential level.

Abstract: A method of communication between a master circuit and two slave circuits over a serial bus wherein: the two slave circuits simultaneously transmit their associated identifiers; the two slave circuits simultaneously transmit the inverse of these identifiers; and each slave circuit exploits the combinations present on the bus to determine an order of communication between the two circuits.

Abstract: A method for electrically programming a non-volatile memory in which a programming cycle includes prior addressing of memory cells from an initial address corresponding to a first row and a column of a memory plane. The method may include addressing the memory cells in a second consecutive row when the end of the first row is reached to store data on bits with consecutive and increasing addresses in two consecutive rows.

Abstract: A method for electrically programming a non-volatile memory in which a programming cycle includes prior addressing of memory cells from an initial address corresponding to a first row and a column of a memory plane. The method may include addressing the memory cells in a second consecutive row when the end of the first row i is reached to store data on bits with consecutive and increasing addresses in two consecutive rows.

Abstract: A method of communication between a master circuit and two slave circuits over a serial bus wherein: the two slave circuits simultaneously transmit their associated identifiers; the two slave circuits simultaneously transmit the inverse of these identifiers; and each slave circuit exploits the combinations present on the bus to determine an order of communication between the two circuits.

Abstract: A memory implementing an incremental address counter is sequentially read. An address jump includes detecting an address jump signal, incrementing the incremental address counter, and reading the content of the memory at the incremented address. The content read at the incremented address is transferred into the incremental address counter, and the content of the memory is read at the address contained in the incremental address counter.

Abstract: In order to reduce the number of lines of a standard bus while, at the same time, preserving the compatibility of the communications protocol, the system uses a modified bus. The modification consists in eliminating two power supply lines and in creating a line assigned to a functional signal that is complementary to one of the functional signals of the system. The supply potentials are regenerated from the functional signal and the complementary signal. The disclosed system can be applied notably to systems using I2C buses such as systems using chip-card readers.

Abstract: A memory implementing an incremental address counter is sequentially read. An address jump includes detecting an address jump signal, incrementing the incremental address counter, and reading the content of the memory at the incremented address. The content read at the incremented address is transferred into the incremental address counter, and the content of the memory is read at the address contained in the incremental address counter.

Abstract: In order to reduce the number of lines of a standard bus while, at the same time, preserving the compatibility of the communications protocol, the system uses a modified bus. The modification consists in eliminating two power supply lines and in creating a line assigned to a functional signal that is complementary to one of the functional signals of the system. The supply potentials are regenerated from the functional signal and the complementary signal. The disclosed system can be applied notably to systems using I2C buses such as systems using chip-card readers.

Abstract: In order to make it possible to ascertain that the programming cycles in an EEPROM type memory have been carried out efficiently, supplementary test cells are provided. A data writing operation is carried out in three successive cycles that consist in the programming of a test cell with a first logic value, a second cycle for the programming of the data elements and a third cycle for the programming of the test cell with a logic value that is complementary to the first one. The state of the test cell enables the detection of power interruptions during programming.

Abstract: To provide efficient protection, in reading mode, of the stored data elements, the integrated circuit has an EEPROM type memory and a lock (L) protecting the zone of the memory. The memory contains a read-protected password (PW) and the circuit has means to release the lock (L) if the circuit receives a write command at the address of the password of the same encrypted password (PW). Application notably to electronic systems and instruments using confidential codes, such as car radios.

Abstract: The use of chip cards, with the level of security of the type associated with chip cards of the type used by banks, is extended to move widespread use by organizing a secure dispatch of blank chip cards to customers wishing to program specific applications therein. The system consists in sending this customer the blank chip card itself and a programming access key to this card, by separate routes. To prevent any additional risks, the access key is itself enciphered and can be deciphered only be a deciphering element in the possession of the customer. The card can then be programmed only if this card is confronted with its deciphering key.