Patents by Inventor Yvon Cordier

Yvon Cordier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230136949
    Abstract: A method for growing a III-V material may include forming at least one layer on a stack including a crystalline layer made of III-V material, a first masking layer surmounting the germination layer, the first masking layer having at least one first opening; depositing a second masking layer covering an upper face of the sacrificial layer; forming at least one second opening in the second masking layer; removing the sacrificial layer selectively at the first masking layer and at the second masking layer; epitaxially growing a material made of the III-V material from the germination layer; forming al least one third opening in the second masking layer; and epitaxially growing at least one material made of the III-V material from the first epitaxial layer.
    Type: Application
    Filed: November 2, 2022
    Publication date: May 4, 2023
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CNRS
    Inventors: Matthew CHARLES, Yvon CORDIER
  • Publication number: 20150221782
    Abstract: A Schottky diode may include a semiconductor substrate having first and second opposing surfaces, and a buffer layer over the first surface of the semiconductor substrate. The Schottky diode may include a first doped GaN layer over the buffer layer and having first and second opposing surfaces, the second surface of the first doped GaN layer being adjacent the buffer layer, and a second doped GaN layer over the second surface of the first doped GaN layer and having a dopant concentration level less than a dopant concentration level of the first doped GaN layer. The buffer layer, the first doped GaN layer, and the second doped GaN layer may define an opening. The Schottky diode may include a first metallization layer being coupled to the semiconductor substrate and to the first surface of the first doped GaN layer and being in the opening.
    Type: Application
    Filed: January 28, 2015
    Publication date: August 6, 2015
    Inventors: Arnaud YVON, Daniel ALQUIER, Yvon Cordier
  • Patent number: 9093271
    Abstract: The invention relates to a method for manufacturing, by means of epitaxy, a monocrystalline layer of GaN on a substrate, wherein the coefficient of thermal expansion is less than the coefficient of thermal expansion of GaN, comprising the following steps: (b) three-dimensional epitaxial growth of a layer of GaN relaxed at the epitaxial temperature, (c1) growth of an intermediate layer of BwAlxGayInzN, (c2) growth of a layer of BwAlxGayInzN, (c3) growth of an intermediate layer of BwAlxGayInzN, at least one of the layers formed in steps (c1) to (c3) being an at least ternary III-N alloy comprising aluminium and gallium, (d) growth of said layer of GaN.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: July 28, 2015
    Assignees: Soitec, Centre National de la Recherche Scientifique (CNRS)
    Inventors: David Schenk, Alexis Bavard, Yvon Cordier, Eric Frayssinet, Mark Kennard, Daniel Rondi
  • Publication number: 20140327013
    Abstract: The invention relates to a method for manufacturing, by means of epitaxy, a monocrystalline layer of GaN on a substrate, wherein the coefficient of thermal expansion is less than the coefficient of thermal expansion of GaN, comprising the following steps: (b) three-dimensional epitaxial growth of a layer of GaN relaxed at the epitaxial temperature, (c1) growth of an intermediate layer of BwAlxGayInzN, growth of a layer of BwAlxGayInzN, (c3) growth of an intermediate layer of BwAlxGayInzN, at least one of the layers formed in steps (c1) to (c3) being an at least ternary III-N alloy comprising aluminium and gallium, (d) growth of said layer of GaN.
    Type: Application
    Filed: June 28, 2012
    Publication date: November 6, 2014
    Applicants: SOITEC, OMMIC, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE (CNRS)
    Inventors: David Schenk, Alexis Bavard, Yvon Cordier, Eric Frayssinet, Mark Kennard, Daniel Rondi
  • Patent number: 7785991
    Abstract: A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: August 31, 2010
    Assignee: STMicroelectronics SA
    Inventors: Sylvain Joblot, Fabrice Semond, Jean Massies, Yvon Cordier, Jean-Yves Duboz
  • Publication number: 20080149936
    Abstract: A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.
    Type: Application
    Filed: November 16, 2007
    Publication date: June 26, 2008
    Applicant: STMICROELECTRONICS SA
    Inventors: SYLVAIN JOBLOT, Fabrice Semond, Jean Massies, Yvon Cordier, Jean-Yves Duboz