Patents by Inventor Yvonne Gawlina
Yvonne Gawlina has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11309410Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive trench of the device for the same gate potential condition.Type: GrantFiled: June 2, 2020Date of Patent: April 19, 2022Assignee: Infineon Technologies AGInventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
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Publication number: 20200295168Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive trench of the device for the same gate potential condition.Type: ApplicationFiled: June 2, 2020Publication date: September 17, 2020Inventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
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Patent number: 10680089Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive gate trench of the device for the same gate potential condition.Type: GrantFiled: June 28, 2019Date of Patent: June 9, 2020Assignee: Infineon Technologies AGInventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
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Publication number: 20190319123Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive gate trench of the device for the same gate potential condition.Type: ApplicationFiled: June 28, 2019Publication date: October 17, 2019Inventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
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Patent number: 10388776Abstract: A semiconductor device includes: a drift region formed in a semiconductor substrate; a body region above the drift region; an active gate trench extending from a first main surface and into the body region and including a first electrode coupled to a gate potential; a source region formed in the body region adjacent to the gate trench and coupled to a source potential; a first body trench extending from the first main surface and into the body region and including a second electrode coupled to the source potential; and an inactive gate trench extending from the first main surface and into the body region and including a third electrode coupled to the gate potential. A conductive channel is present along the active gate trench when the gate potential is at an on-voltage, whereas no conductive channel is present along the inactive gate trench for the same gate potential condition.Type: GrantFiled: November 13, 2018Date of Patent: August 20, 2019Assignee: Infineon Technologies AGInventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
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Publication number: 20190103480Abstract: A semiconductor device includes: a drift region formed in a semiconductor substrate; a body region above the drift region; an active gate trench extending from a first main surface and into the body region and including a first electrode coupled to a gate potential; a source region formed in the body region adjacent to the gate trench and coupled to a source potential; a first body trench extending from the first main surface and into the body region and including a second electrode coupled to the source potential; and an inactive gate trench extending from the first main surface and into the body region and including a third electrode coupled to the gate potential. A conductive channel is present along the active gate trench when the gate potential is at an on-voltage, whereas no conductive channel is present along the inactive gate trench for the same gate potential condition.Type: ApplicationFiled: November 13, 2018Publication date: April 4, 2019Inventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
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Patent number: 10153339Abstract: A semiconductor device includes a common doping region located within a semiconductor substrate of the semiconductor device. The common doping region includes a first portion. A maximal doping concentration within the first portion is higher than 1·1015 cm?3. The common doping region includes a second portion. A minimal doping concentration within the second portion is lower than 50% of the maximal doping concentration within the first portion of the common doping region. The common doping region includes a third portion. A minimal doping concentration within the third portion is more than 30% higher than the minimal doping concentration within the second portion. The second portion of the common doping region is located vertically between the first portion of the common doping region and the third portion of the common doping region.Type: GrantFiled: September 19, 2017Date of Patent: December 11, 2018Assignee: Infineon Technologies AGInventors: Stephan Voss, Alexander Breymesser, Hans-Joachim Schulze, Yvonne Gawlina-Schmidl
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Patent number: 10134885Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.Type: GrantFiled: May 12, 2017Date of Patent: November 20, 2018Assignee: Infineon Technologies AGInventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
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Publication number: 20180090565Abstract: A semiconductor device includes a common doping region located within a semiconductor substrate of the semiconductor device. The common doping region includes a first portion. A maximal doping concentration within the first portion is higher than 1·1015 cm?3. The common doping region includes a second portion. A minimal doping concentration within the second portion is lower than 50% of the maximal doping concentration within the first portion of the common doping region. The common doping region includes a third portion. A minimal doping concentration within the third portion is more than 30% higher than the minimal doping concentration within the second portion. The second portion of the common doping region is located vertically between the first portion of the common doping region and the third portion of the common doping region.Type: ApplicationFiled: September 19, 2017Publication date: March 29, 2018Inventors: Stephan Voss, Alexander Breymesser, Hans-Joachim Schulze, Yvonne Gawlina-Schmidl
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Publication number: 20170250271Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.Type: ApplicationFiled: May 12, 2017Publication date: August 31, 2017Inventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
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Patent number: 9680005Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.Type: GrantFiled: August 12, 2015Date of Patent: June 13, 2017Assignee: Infineon Technologies AGInventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
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Publication number: 20150349116Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.Type: ApplicationFiled: August 12, 2015Publication date: December 3, 2015Inventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
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Patent number: 9142655Abstract: A semiconductor device in a semiconductor substrate includes a first main surface and a transistor cell. The transistor cell includes a drift region of a first conductivity type, a body region of a second conductivity type between the drift region and the first main surface, an active trench in the first main surface extending to the drift region, a source region of the first conductivity in the body region adjacent to the active trench, and a body trench at the first main surface extending to the drift region and adjacent to the body region and the drift region. The active trench includes a gate insulating layer at sidewalls and a bottom side, and a gate conductive layer. The body trench includes a conductive layer and an insulating layer at sidewalls and a bottom side, and asymmetric to a perpendicular axis of the first main surface and the body trench center.Type: GrantFiled: March 12, 2013Date of Patent: September 22, 2015Assignee: Infineon Technologies AGInventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
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Patent number: 9054151Abstract: A semiconductor device includes a semiconductor body including a first surface having a normal direction defining a vertical direction, a first n-type semiconductor region arranged below the first surface and having a first maximum doping concentration and a second n-type semiconductor region arranged below the first n-type semiconductor region and including, in a vertical cross-section, two spaced apart first n-type portions each adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and having a first minimum distance to the first surface, and a second n-type portion adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and a second minimum distance to the first surface which is larger than the first minimum distance. A p-type second semiconductor layer forms a pn-junction with the second n-type portion.Type: GrantFiled: October 15, 2013Date of Patent: June 9, 2015Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina
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Patent number: 8853774Abstract: A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.Type: GrantFiled: November 30, 2012Date of Patent: October 7, 2014Assignee: Infineon Technologies AGInventors: Maria Cotorogea, Hans Peter Felsl, Yvonne Gawlina, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Georg Seibert, Andre Rainer Stegner, Wolfgang Wagner
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Publication number: 20140264432Abstract: A semiconductor device in a semiconductor substrate includes a first main surface and a transistor cell. The transistor cell includes a drift region of a first conductivity type, a body region of a second conductivity type between the drift region and the first main surface, an active trench in the first main surface extending to the drift region, a source region of the first conductivity in the body region adjacent to the active trench, and a body trench at the first main surface extending to the drift region and adjacent to the body region and the drift region. The active trench includes a gate insulating layer at sidewalls and a bottom side, and a gate conductive layer. The body trench includes a conductive layer and an insulating layer at sidewalls and a bottom side, and asymmetric to a perpendicular axis of the first main surface and the body trench center.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Inventors: Maria Cotorogea, Frank Wolter, Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina-Schmidl
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Publication number: 20140151789Abstract: A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.Type: ApplicationFiled: November 30, 2012Publication date: June 5, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Maria Cotorogea, Hans Peter Felsl, Yvonne Gawlina, Francisco Javier Santos Rodriguez, Hans-Joachim Schulze, Georg Seibert, Andre Rainer Stegner, Wolfgang Wagner
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Publication number: 20140034998Abstract: A semiconductor device includes a semiconductor body including a first surface having a normal direction defining a vertical direction, a first n-type semiconductor region arranged below the first surface and having a first maximum doping concentration and a second n-type semiconductor region arranged below the first n-type semiconductor region and including, in a vertical cross-section, two spaced apart first n-type portions each adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and having a first minimum distance to the first surface, and a second n-type portion adjoining the first n-type semiconductor region, having a maximum doping concentration which is higher than the first maximum doping concentration and a second minimum distance to the first surface which is larger than the first minimum distance. A p-type second semiconductor layer forms a pn-junction with the second n-type portion.Type: ApplicationFiled: October 15, 2013Publication date: February 6, 2014Applicant: Infineon Technologies AGInventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina
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Patent number: 8587025Abstract: A method for forming a laterally varying n-type doping concentration is provided. The method includes providing a semiconductor wafer with a first surface, a second surface arranged opposite to the first surface and a first n-type semiconductor layer having a first maximum doping concentration, implanting protons of a first maximum energy into the first n-type semiconductor layer, and locally treating the second surface with a masked hydrogen plasma. Further, a semiconductor device is provided.Type: GrantFiled: July 3, 2012Date of Patent: November 19, 2013Assignee: Infineon Technologies AGInventors: Hans-Joachim Schulze, Franz-Josef Niedernostheide, Yvonne Gawlina