Abstract: Some embodiments relate to a device disposed on a semiconductor substrate. The semiconductor substrate includes a base region and a crown structure extending upwardly from the base region. The crown structure is narrower than the base region. A plurality of fins extend upwardly from an upper surface of the crown structure. A gate dielectric material is disposed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode is disposed along sidewall portions of the gate dielectric material. An uppermost surface of the conductive electrode resides below the upper surfaces of the plurality of fins.

Abstract: Some embodiments relate to a device disposed on a semiconductor substrate. The semiconductor substrate includes a base region and a crown structure extending upwardly from the base region. The crown structure is narrower than the base region. A plurality of fins extend upwardly from an upper surface of the crown structure. A gate dielectric material is disposed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode is disposed along sidewall portions of the gate dielectric material. An uppermost surface of the conductive electrode resides below the upper surfaces of the plurality of fins.

Abstract: Some embodiments relate to a method. A semiconductor substrate is provided and has a base region and a crown structure extending upwardly from the base region. A plurality of fins are formed to extend upwardly from an upper surface of the crown structure. A gate dielectric material is formed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode material is formed over upper surfaces and sidewalls of the gate dielectric material. An etch is performed to etch back the conductive electrode material so upper surfaces of etched back conductive electrodes reside below the upper surfaces of the plurality of fins.

Abstract: Some embodiments relate to a two transistor band gap reference circuit. A first transistor includes a first source, a first drain, a first body region separating the first source from the first drain, and a first gate. The first drain and first gate are coupled to a DC supply terminal. The second transistor includes a second source, a second drain, a second body region separating the second source from the second drain, and a second gate. The second gate is coupled to the DC supply terminal, and the second drain is coupled to the first source. Body bias circuitry is configured to apply a body bias voltage to at least one of the first and second body regions. Other embodiments relate to FinFET devices.

Abstract: Some embodiments relate to a method. A semiconductor substrate is provided and has a base region and a crown structure extending upwardly from the base region. A plurality of fins are formed to extend upwardly from an upper surface of the crown structure. A gate dielectric material is formed over upper surfaces and sidewalls of the plurality of the fins. A conductive electrode material is formed over upper surfaces and sidewalls of the gate dielectric material. An etch is performed to etch back the conductive electrode material so upper surfaces of etched back conductive electrodes reside below the upper surfaces of the plurality of fins.

Abstract: Some embodiments relate to a two transistor band gap reference circuit. A first transistor includes a first source, a first drain, a first body region separating the first source from the first drain, and a first gate. The first drain and first gate are coupled to a DC supply terminal. The second transistor includes a second source, a second drain, a second body region separating the second source from the second drain, and a second gate. The second gate is coupled to the DC supply terminal, and the second drain is coupled to the first source. Body bias circuitry is configured to apply a body bias voltage to at least one of the first and second body regions. Other embodiments relate to FinFET devices.

Abstract: A fastening arrangement comprises a first fastening member connected to a first strap and a second fastening member connected to a second strap. The first fastening member includes a first surface comprising at least one first interlocking member. The second fastening member includes a channel positioned between a second surface and a biasing member. The channel is configured to receive the first fastening member with the first surface facing the second surface. The second surface includes at least one second interlocking member configured to engage the first interlocking member in a manner that blocks the first interlocking member from moving relative to the second interlocking member in at least one direction. The biasing member is configured to urge the first interlocking member into engagement with the second interlocking member when the first fastening member is inserted into the channel of the second fastening member.

Abstract: A capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures of the plurality of cell structures each includes a first capacitor electrode, a second capacitor electrode over the first capacitor electrode, a third capacitor electrode adjacent to first sidewalls of the first and second capacitor electrodes, a fourth capacitor electrode adjacent to second sidewalls of the first and second capacitor electrodes, and a fifth capacitor electrode adjacent to the fourth capacitor electrode.

Abstract: An integrated circuit includes a first circuit. The first circuit includes a first transistor having a first dopant type. The first circuit further includes a first cascode transistor having the first dopant type, wherein the first cascode transistor connected in series with the first transistor. The first circuit further includes a second transistor having a second dopant type opposite to the first dopant type, wherein the second transistor is connected in series with the first transistor. The first circuit includes a second cascode transistor having the second dopant type, wherein the second cascode transistor is connected in series with the second transistor. The integrated circuit further includes a first bias circuit configured to adjust a threshold voltage of at least one of the first cascode transistor or the second cascode transistor.

Abstract: A capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures of the plurality of cell structures each includes a first capacitor electrode, a second capacitor electrode over the first capacitor electrode, a third capacitor electrode adjacent to first sidewalls of the first and second capacitor electrodes, a fourth capacitor electrode adjacent to second sidewalls of the first and second capacitor electrodes, and a fifth capacitor electrode adjacent to the fourth capacitor electrode.

Abstract: A charge pump has at least one charge pump stage. Each charge pump stage includes at least one NMOS device. The at least one NMOS device has a deep N-well (DNW), a gate and a drain, and is coupled to at least one capacitor, a first node, a second node and a switch. For the at least one NMOS device, the gate is capable of receiving a different signal from the drain. The first node is arranged to receive an input signal. The switch is coupled between the at least one NMOS device and a ground. A drain of the switch is coupled to a deep N-well of the switch. The at least one capacitor is arranged to store electrical charges. The charge pump stage is configured to supply the electrical charges to the second node. The DNW is coupled to the ground for a negative pump operation.

Abstract: An integrated circuit includes at least one memory array and at least one capacitor array over a substrate. The at least one capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures of the plurality of cell structures comprise a first capacitor electrode over the substrate. A second capacitor electrode is over the first capacitor electrode. A third capacitor electrode is adjacent to first sidewalls of the first and second capacitor electrodes. A fourth capacitor electrode is adjacent to second sidewalls of the first and second capacitor electrodes. A fifth capacitor electrode is over the substrate and adjacent to the fourth capacitor electrode.

Abstract: A FLASH memory cell includes a control gate over a floating gate over a substrate. A wall line and an erase gate each is disposed adjacent to a respective sidewall of the control gate. A first source/drain (S/D) region is disposed in the substrate and adjacent to a sidewall of the wall line. A second S/D region is disposed in the substrate and adjacent to the sidewall of the floating gate. A method of operating the FLASH memory cell includes applying a first voltage level to the control gate. A second voltage level is applied to the word line. The second voltage level is lower than the first voltage level. A third voltage level is applied to the first S/D region. A fourth voltage level is applied to the second S/D region. The fourth voltage level is higher than the third voltage level. The erase gate is electrically floating.

Abstract: A fastening arrangement comprises a first fastening member connected to a first strap and a second fastening member connected to a second strap. The first fastening member includes a first surface comprising at least one first interlocking member. The second fastening member includes a channel positioned between a second surface and a biasing member. The channel is configured to receive the first fastening member with the first surface facing the second surface. The second surface includes at least one second interlocking member configured to engage the first interlocking member in a manner that blocks the first interlocking member from moving relative to the second interlocking member in at least one direction. The biasing member is configured to urge the first interlocking member into engagement with the second interlocking member when the first fastening member is inserted into the channel of the second fastening member.

Abstract: An integrated circuit includes at least one memory array and at least one capacitor array over a substrate. The at least one capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures of the plurality of cell structures comprise a first capacitor electrode over the substrate. A second capacitor electrode is over the first capacitor electrode. A third capacitor electrode is adjacent to first sidewalls of the first and second capacitor electrodes. A fourth capacitor electrode is adjacent to second sidewalls of the first and second capacitor electrodes. A fifth capacitor electrode is over the substrate and adjacent to the fourth capacitor electrode.

Abstract: An integrated circuit includes a first circuit. The first circuit includes a first transistor having a first dopant type. The first circuit further includes a first cascode transistor having the first dopant type, wherein the first cascode transistor connected in series with the first transistor. The first circuit further includes a second transistor having a second dopant type opposite to the first dopant type, wherein the second transistor is connected in series with the first transistor. The first circuit includes a second cascode transistor having the second dopant type, wherein the second cascode transistor is connected in series with the second transistor. The integrated circuit further includes a first bias circuit configured to adjust a threshold voltage of at least one of the first cascode transistor or the second cascode transistor.

Abstract: A fastening arrangement comprises a first fastening member connected to a first strap and a second fastening member connected to a second strap. The first fastening member includes a first surface comprising at least one first interlocking member. The second fastening member includes a channel positioned between a second surface and a biasing member. The channel is configured to receive the first fastening member with the first surface facing the second surface. The second surface includes at least one second interlocking member configured to engage the first interlocking member in a manner that blocks the first interlocking member from moving relative to the second interlocking member in at least one direction. The biasing member is configured to urge the first interlocking member into engagement with the second interlocking member when the first fastening member is inserted into the channel of the second fastening member.

Abstract: A method includes receiving a first voltage at a first input circuit of a bi-directional charge pump circuit, selectively turning on a first switch of a switching circuit that is coupled electrically to a deep N-well transistor of a first set of one or more intermediate pump stages that are coupled between the first input circuit and a first output circuit, and providing a third voltage from the first output circuit in response to receiving a second voltage at an input of a first diode of the output circuit from the first set of the one or more intermediate pump stages.

Abstract: A charge pump has at least one charge pump stage. Each charge pump stage includes at least one NMOS device. The at least one NMOS device has a deep N-well (DNW), a gate and a drain, and is coupled to at least one capacitor, a first node, a second node and a switch. For the at least one NMOS device, the gate is capable of receiving a different signal from the drain. The first node is arranged to receive an input signal. The switch is coupled between the at least one NMOS device and a ground. A drain of the switch is coupled to a deep N-well of the switch. The at least one capacitor is arranged to store electrical charges. The charge pump stage is configured to supply the electrical charges to the second node. The DNW is coupled to the ground for a negative pump operation.

Abstract: An integrated circuit includes at least one FLASH memory array and at least one capacitor array disposed over a substrate. The at least one capacitor array includes a plurality of capacitor cell structures. The capacitor cell structures each includes a first capacitor electrode disposed over the substrate. A second capacitor electrode is disposed over the first capacitor electrode. A third capacitor electrode is disposed adjacent to first sidewalls of the first and second capacitor electrodes. A fourth capacitor electrode is disposed adjacent to second sidewalls of the first and second capacitor electrodes.