Abstract: A power module includes at least one electrically conductive power substrate; and a plurality of power devices arranged on and connected to the at least one electrically conductive power substrate. The power module further includes at least one elevated signal element electrically connected to the plurality of power devices and/or at least one elevated power plane electrically connected to the at least one electrically conductive power substrate and electrically connected to the plurality of power devices.

Abstract: A power module includes at least one power substrate; a plurality of power devices arranged on the at least one power substrate; and a power connector configured to be electrically connected to the plurality of power devices. The power connector includes a mechanically compliant fitting.

Abstract: A power component configured to improve partial discharge performance includes at least one terminal that includes a first planar surface, a second planar surface opposite the first planar surface, and a curved surface extending from the first planar surface to the second planar surface. The power component may include at least one of the following: a power module or a buss bar.

Abstract: A process includes measuring at least one component parameter of a plurality of components with a testing device; and arranging at least a portion of the plurality of components in a sequential order based on the at least one component parameter with an implementation system in at least one of the following: a shipping format and a device implementation of the portion of the plurality of components. A system is disclosed as well.

Abstract: A power module includes at least one electrically conductive power substrate; and a plurality of power devices arranged on and connected to the at least one electrically conductive power substrate. The power module further includes at least one elevated signal element electrically connected to the plurality of power devices and/or at least one elevated power plane electrically connected to the at least one electrically conductive power substrate and electrically connected to the plurality of power devices.

Abstract: Provided is a double-sided cooling structure for a semiconductor device using a low processing temperature and reduced processing time utilizing solid phase diffusion bonding. The fabrication method for this system is provided. The semiconductor device 1 comprising: a mounting substrate 70; a semiconductor chip 10 disposed on the mounting substrate 70 and a semiconductor substrate 26, a source pad electrode SP and a gate pad electrode GP disposed on a surface of the semiconductor substrate 26, and a drain pad electrode 36 disposed on a back side surface of the semiconductor substrate 26 to be contacted with the mounting substrate 70; and a source connector SC disposed on the source pad electrode SP. The mounting substrate 70 and the drain pad electrode 36 are bonded by using solid phase diffusion bonding.

Abstract: A multichip power module directly connecting the busboard to a printed-circuit board that is attached to the power substrate enabling extremely low loop inductance for extreme environments such as high temperature operation. Wire bond interconnections are taught from the power die directly to the busboard further enabling enable low parasitic interconnections. Integration of on-board high frequency bus capacitors provide extremely low loop inductance. An extreme environment gate driver board allows close physical proximity of gate driver and power stage to reduce overall volume and reduce impedance in the control circuit. Parallel spring-loaded pin gate driver PCB connections allows a reliable and reworkable power module to gate driver interconnections.

Abstract: Provided is a double-sided cooling structure for a semiconductor device using a low processing temperature and reduced processing time utilizing solid phase diffusion bonding. The fabrication method for this system is provided. The semiconductor device 1 comprising: a mounting substrate 70; a semiconductor chip 10 disposed on the mounting substrate 70 and a semiconductor substrate 26, a source pad electrode SP and a gate pad electrode GP disposed on a surface of the semiconductor substrate 26, and a drain pad electrode 36 disposed on a back side surface of the semiconductor substrate 26 to be contacted with the mounting substrate 70; and a source connector SC disposed on the source pad electrode SP. The mounting substrate 70 and the drain pad electrode 36 are bonded by using solid phase diffusion bonding.