Abstract: An apparatus and method for plating magnetic cores by periodically transferring a plate directly back and forth between a metal plating environment and an insulation deposit environment. This direct metal to insulation to metal plating is enabled by a nano-scale insulation layer that provides an imperfect coverage of the metal layer while still keeping sufficient insulation to prevent eddy current formation—even during high-frequency current applications. Therefore, this invention enables the practical creation of magnetic cores having layers with widths even under one nanometer and can generate cores having a layer scale that can be varied to suit a variety of uses in the microelectronic industry.

Abstract: A hybrid conductive material comprising at least one conductive material having at least one internal porous insulative layer; and wherein, at least one of the conductive materials fills the voids of the internal porous insulative layer. The hybrid material blends conductive metals and porous insulation layers in a manner so that the resulting material operates as a single layer material with its own unique conductivity and skin depth; and a unique and strong directional impedance. By using a porous insulation layer, metal layers may be bonded together through insulation layers, and this allows rapid low-cost formation of the hybrid material. The hybrid material may be used to form thin wires or traces capable of handling high frequency applications.

Abstract: An apparatus and method for plating magnetic cores by periodically transferring a plate directly back and forth between a metal plating environment and an insulation deposit environment. This direct metal to insulation to metal plating is enabled by a nano-scale insulation layer that provides an imperfect coverage of the metal layer while still keeping sufficient insulation to prevent eddy current formation—even during high-frequency current applications. Therefore, this invention enables the practical creation of magnetic cores having layers with widths even under one nanometer and can generate cores having a layer scale that can be varied to suit a variety of uses in the microelectronic industry.