Abstract: A computer memory system comprises non-volatile memory and a memory controller module including a memory controller. The memory controller module is selectively secured in a memory module socket of a motherboard to provide the memory controller in communication with a memory module bus using a memory bus standard. The memory controller includes one or more ports for communication with the non-volatile memory using a data storage protocol, wherein the memory controller controls read and write operations for the non-volatile memory. The memory system further comprises one or more cables connecting the one or more ports of the memory controller to the non-volatile memory, wherein the non-volatile memory is not on the memory controller module. Optionally, the non-volatile memory may be included in a separate memory module or a solid state drive.

Abstract: An apparatus for encrypting processor related noise is disclosed. A method and a computer program product also perform the functions of the apparatus. The apparatus includes a frequency selection module that selects frequencies for a first noise output. The frequencies are within a range of frequencies of a second noise output. The second noise output is produced by one or more first voltage regulating modules providing power to a processor. The apparatus includes an amplitude selection module that selects an amplitude for each frequency of the first noise output. The apparatus includes a noise scrambling module that produces the first noise output based on one or both of the frequency selection module and the amplitude selection module. The first noise output combines with the second noise output to produce a third noise output such that coherence between the third noise output and operations of the processor is below a threshold.

Abstract: An apparatus for encrypting processor related noise is disclosed. A method and a computer program product also perform the functions of the apparatus. The apparatus includes a frequency selection module that selects frequencies for a first noise output. The frequencies are within a range of frequencies of a second noise output. The second noise output is produced by one or more first voltage regulating modules providing power to a processor. The apparatus includes an amplitude selection module that selects an amplitude for each frequency of the first noise output. The apparatus includes a noise scrambling module that produces the first noise output based on one or both of the frequency selection module and the amplitude selection module. The first noise output combines with the second noise output to produce a third noise output such that coherence between the third noise output and operations of the processor is below a threshold.

Abstract: A transversely actuated piezoelectric bellows heatsink (TAPBH) has a linkage that includes multiple rigid sections coupled by flexible joints. A first fixed support is affixed to a first end of the linkage, and a piezoelectric element is mechanically coupled to a second end of the linkage. A diaphragm is mechanically affixed to a first side of the linkage, and an air enclosure, having an open area, is affixed to the diaphragm. A second fixed support is mechanically affixed to a second side of the linkage. Cyclic power from the power supply causes the piezoelectric element to expand and contract to force the linkage to expand and contract in an analogous manner, thus causing the diaphragm to move in an amplified motion to cause air to enter and be expelled from the air enclosure via air valves.

Abstract: A transversely actuated piezoelectric bellows heatsink (TAPBH) has a linkage that includes multiple rigid sections coupled by flexible joints. A first fixed support is affixed to a first end of the linkage, and a piezoelectric element is mechanically coupled to a second end of the linkage. A diaphragm is mechanically affixed to a first side of the linkage, and an air enclosure, having an open area, is affixed to the diaphragm. A second fixed support is mechanically affixed to a second side of the linkage. Cyclic power from the power supply causes the piezoelectric element to expand and contract to force the linkage to expand and contract in an analogous manner, thus causing the diaphragm to move in an amplified motion to cause air to enter and be expelled from the air enclosure via air valves.

Abstract: A universal press-fit connection allows a component having a connector pin to be connected to a compatible plated through hole of a circuit board regardless of circuit board thickness. The connector pin includes a proximate end adjacent the component, a distal end with a fork lock, and a compliant portion between the proximate and distal ends. A multi-width through hole includes a first portion partially extending through the circuit board and a second, wider portion extending beyond the first portion. The fork lock initially moves radially inward upon insertion into the first portion via flexing of the compliant portion, and re-expands when entering the second portion. The compliant portion engages the through hole and the fork lock secures the connector pin in the through hole.

Abstract: Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights.

Abstract: An electronic component is connected to a circuit board by forming a connector pin on the electronic component, the connector pin having a proximate end secured to the electronic component, a distal end with a fork lock, and a compliant portion between the proximate and distal ends. A multi-width through-hole is formed on a circuit board having a circuit board thickness greater than a length of the connector pin, with a first portion that is narrower than each of the compliant portion and the fork lock and extends partially through the circuit board and a second portion that extends beyond the first portion and is wider than the first portion. The connector pin is inserted into the first portion of the through-hole and the fork lock is moved beyond the first portion into the second portion of the through-hole.

Abstract: A universal press-fit connection allows a component having a connector pin to be connected to a compatible plated through hole of a circuit board regardless of circuit board thickness. The connector pin includes a proximate end adjacent the component, a distal end with a fork lock, and a compliant portion between the proximate and distal ends. A multi-width through hole includes a first portion partially extending through the circuit board and a second, wider portion extending beyond the first portion. The fork lock initially moves radially inward upon insertion into the first portion via flexing of the compliant portion, and re-expands when entering the second portion. The compliant portion engages the through hole and the fork lock secures the connector pin in the through hole.

Abstract: Dual heat sinks, apparatuses, and methods for installing a dual heat sink for distributing a thermal load are provided. Embodiments include a top base to couple with a first integrated circuit of a first board and to receive a first thermal load from the first integrated circuit; a bottom base to couple with a second integrated circuit of a second board and to receive a second thermal load from the second integrated circuit; and a thermal dissipating structure coupled between the top base and the bottom base, the thermal dissipating structure to receive and distribute the first thermal load and the second thermal load from the top base and the bottom base; wherein a height of the thermal dissipating structure is adjustable so as to change a distance separating the top base and the bottom base.

Abstract: Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights.

Abstract: Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights.

Abstract: Methods, apparatus, and products for detecting an increase in thermal resistance of a heat sink in a computer system, the heat sink dissipating heat for a component of the computer system, the computer system including a fan controlling airflow across the heat sink, the computer system also including a temperature monitoring device, including: measuring, by a monitoring module through use of the temperature monitoring device during operation of the computer system, thermal resistance of the heat sink; determining whether the measured thermal resistance of the heat sink is greater than a threshold thermal resistance, the threshold thermal resistance stored in a thermal profile in non-volatile memory, and if the measured thermal resistance of the heat sink is greater than the threshold thermal resistance, notifying a system administrator.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory switching data processing system is provided. The memory switching data processing system includes one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.

Abstract: A memory switching data processing system including one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.

Abstract: Methods, apparatus, and products for detecting an increase in thermal resistance of a heat sink in a computer system, the heat sink dissipating heat for a component of the computer system, the computer system including a fan controlling airflow across the heat sink, the computer system also including a temperature monitoring device, including: measuring, by a monitoring module through use of the temperature monitoring device during operation of the computer system, thermal resistance of the heat sink; determining whether the measured thermal resistance of the heat sink is greater than a threshold thermal resistance, the threshold thermal resistance stored in a thermal profile in non-volatile memory, and if the measured thermal resistance of the heat sink is greater than the threshold thermal resistance, notifying a system administrator.

Abstract: Methods, apparatus, and products are disclosed for optimizing a physical data communications topology between a plurality of computing nodes, the physical data communications topology including physical links configured to connect the plurality of nodes for data communications, that include carrying out repeatedly at a predetermined pace: detecting network packets transmitted through the links between each pair of nodes in the physical data communications topology, each network packet characterized by one or more packet attributes; assigning, to each network packet, a packet weight in dependence upon the packet attributes for that network packet; determining, for each pair of nodes in the physical data communications topology, a node pair traffic weight in dependence upon the packet weights assigned to the network packets transferred between that pair of nodes; and reconfiguring the physical links between each pair of nodes in dependence upon the node pair traffic weights.

Abstract: The invention is directed to providing a virtualized blade flash with a management module in a blade server. A method of configuring a blade server according to an embodiment of the invention includes: providing a plurality of blades, wherein each blade comprising: a service processor; a chip set; an at least one central processing unit (CPU); providing a management module in communication with each of the plurality of blades; and adding a virtual flash store at the management module.

Abstract: A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a memory switching data processing system is provided. The memory switching data processing system includes one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.

Abstract: A memory switching data processing system including one or more central processing units (‘CPUs’); random access memory organized in at least two banks of memory modules; one or more memory buses providing communications paths for data among the CPUs and the memory modules; and a flexibly configurable memory bus switch comprising a first configuration adapting the first CPU to a first bank of memory modules and a second CPU to a second bank of memory modules and a second configuration adapting the first CPU to both the first bank of memory modules and the second bank of memory modules.