Abstract: A method for operating a computing system includes determining a baseline accuracy of the computing system based on a baseline data transmission format comprising a baseline quantity of data bits and a baseline quantity of error correction (ECC) bits, determining sample accuracies of the computing system based on sample data transmission formats each including a quantity of data bits and a quantity of ECC bits that are different from the baseline quantity of data bits and the baseline quantity of ECC bits, and storing data in a memory device of the computing system using at least one data transmission format, wherein the at least one data transmission format is selected from a group of data transmission formats comprising the baseline data transmission format and the sample data transmission formats and the at least one data transmission is selected based on the baseline accuracy and the sample accuracies.

Abstract: A DRAM fabrication process for producing a semiconductor die adapted for having the ability to be both a hybrid memory and power supply capacitance. DRAM arrays on a semiconductor die may be individually selected to function as either a memory or as supplemental capacitance on a power distribution network serving circuits on one or more semiconductor dice in a three-dimensional active-on-active (AoA) stacked semiconductor die package configuration. Defective DRAM array trench capacitors can be repurposed to serve as supplemental capacitance on a power distribution network. DRAM array trench capacitors can be dynamically reassigned as supplemental capacitance when power supply monitors sense that additional power supply capacitance is needed.

Abstract: Embodiments herein describe a 3D stack of dies (e.g., an active-on-active (AoA) stack) with a connectivity die that enables the decoupling of processing regions in coupled dies from each other and from the physical location of I/O blocks on an I/O die. For example, the first die may have a plurality of hardware processing blocks that are arranged in a regular manner (e.g., an array with rows and columns). The connectivity die can include interconnects that couple these hardware processing blocks to I/O blocks in a second die. These I/O blocks may be arranged in an irregular manner. The interconnects in the connectivity die can provide fair access so that processing blocks on a first side of the first die can access an I/O block on the opposite side of the second die without using resources for neighboring processing blocks.

Abstract: The embodiments herein rely on cross reticle wires (also referred to as cross die wires) to provide communication channels between programmable dies already formed on a wafer. Using cross reticle wires to facilitate x-die communication can be three to four orders of magnitude faster than using general purpose I/O. With a wafer containing cross reticle wires, various device geometries can be generated at dicing time by cutting across different reticle boundaries. This allows up to full wafer-size devices, or several smaller sub-wafer devices to be derived from one wafer. Although the programmable dies can contain defects, these defects can be identified and avoided when generating a bitstream for configuring programmable features in the programmable dies.

Abstract: An integrated circuit can include a Network-on-Chip (NoC) having a router network with first and second shared physical channels. The NoC includes one or more master bridge circuits (MBCs) coupled to the router network, where each MBC provides a packet-based interface to a master client circuit coupled thereto for initiating transactions over the router network. Each MBC sends and receives data for the transactions over the router network as flits of packets according to a schedule. The NoC includes one or more slave bridge circuits (SBCs) coupled to the router network, where each SBC provides a packet-based interface to a slave client circuit coupled thereto to for responding to the transactions over the router network. Each SBC sends and receives the flits over the router network according to the schedule. The flits sent from different client circuits are interleaved using time-multiplexing on the first and second shared physical channels.

Abstract: The present disclosure includes systems and methods relating to information flow and analyzing faults in integrated circuits for digital devices and microprocessor systems. In general, one implementation, involves a technique including: receiving a hardware design specifying an implementation for information flow in a hardware configuration; receiving one or more labels annotating the hardware design; receiving one or more fault properties specifying at least a fault type relating to the one or more labels for implementing an information flow model indicating a fault path in the hardware configuration; determining, for each of the one or more fault properties, a label value by translating the fault property into the information flow model; and automatically assigning a respective label value to each of the one or more labels in the hardware design.

Abstract: The present disclosure includes systems and methods relating to information flow and analyzing faults in integrated circuits for digital devices and microprocessor systems. In general, one implementation, involves a technique including: receiving a hardware design specifying an implementation for information flow in a hardware configuration; receiving one or more labels annotating the hardware design; receiving one or more fault properties specifying at least a fault type relating to the one or more labels for implementing an information flow model indicating a fault path in the hardware configuration; determining, for each of the one or more fault properties, a label value by translating the fault property into the information flow model; and automatically assigning a respective label value to each of the one or more labels in the hardware design.