Abstract: A device and method are presented. Largest and smallest successful values of a receive clock delay and a transmit clock delay are determined. A first set of parameters for an SPI coupled to a DDR flash memory are set, including the largest successful values of the transmit clock delay and the receive clock delay, and a first value of a RD cycle. A second set of parameters for the SPI are set, including the smallest successful value of the transmit clock delay and receive clock delay, and a second value of the RD cycle. One of the first and second sets of parameters is selected based on whether the first or second set of parameters results in successfully reading from the DDR flash memory over a larger range of operating temperatures. The SPI is programmed using the selected one of the first and second sets of parameters.

Abstract: A device and method are presented. Largest and smallest successful values of a receive clock delay and a transmit clock delay are determined. A first set of parameters for an SPI coupled to a DDR flash memory are set, including the largest successful values of the transmit clock delay and the receive clock delay, and a first value of a RD cycle. A second set of parameters for the SPI are set, including the smallest successful value of the transmit clock delay and receive clock delay, and a second value of the RD cycle. One of the first and second sets of parameters is selected based on whether the first or second set of parameters results in successfully reading from the DDR flash memory over a larger range of operating temperatures. The SPI is programmed using the selected one of the first and second sets of parameters.