Patents by Inventor Zachary Matthew Stum

Zachary Matthew Stum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9601332
    Abstract: A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: March 21, 2017
    Assignee: General Electric Company
    Inventors: Zachary Matthew Stum, Reza Ghandi
  • Publication number: 20160307997
    Abstract: A semiconductor device may include a substrate comprising silicon carbide; a drift layer disposed over the substrate doped with a first dopant type; an anode region disposed adjacent to the drift layer, wherein the anode region is doped with a second dopant type; and a junction termination extension disposed adjacent to the anode region and extending around the anode region, wherein the junction termination extension has a width and comprises a plurality of discrete regions separated in a first direction and in a second direction and doped with varying concentrations with the second dopant type, so as to have an effective doping profile of the second conductivity type of a functional form that generally decreases along a direction away from an edge of the primary blocking junction.
    Type: Application
    Filed: June 28, 2016
    Publication date: October 20, 2016
    Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Peter Almern Losee, Kevin Sean Motocha, Richard Joseph Saia, Zachary Matthew Stum, Ljuibisa Dragolijub Stevanovic, Kuna Venkat Satya Rama Kishore, James William Kretchmer
  • Patent number: 9406762
    Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: August 2, 2016
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Peter Almern Losee, Kevin Sean Matocha, Richard Joseph Saia, Zachary Matthew Stum, Ljubisa Dragoljub Stevanovic, Kuna Venkat Satya Rama Kishore, James William Kretchmer
  • Publication number: 20160118258
    Abstract: A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.
    Type: Application
    Filed: January 4, 2016
    Publication date: April 28, 2016
    Inventors: Zachary Matthew STUM, Reza GHANDI
  • Patent number: 9230807
    Abstract: A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 5, 2016
    Assignee: General Electric Company
    Inventors: Zachary Matthew Stum, Reza Ghandi
  • Publication number: 20150236151
    Abstract: A semiconductor device is presented. The device includes a semiconductor layer including silicon carbide, and having a first surface and a second surface. A gate insulating layer is disposed on a portion of the first surface of the semiconductor layer, and a gate electrode is disposed on the gate insulating layer. The device further includes an oxide disposed between the gate insulating layer and the gate electrode at a corner adjacent an edge of the gate electrode so as the gate insulating layer has a greater thickness at the corner than a thickness at a center of the layer. A method for fabricating the device is also provided.
    Type: Application
    Filed: February 18, 2014
    Publication date: August 20, 2015
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: James Jay McMahon, Ljubisa Dragoljub Stevanovic, Stephen Daley Arthur, Thomas Bert Gorczyca, Richard Alfred Beaupre, Zachary Matthew Stum, Alexander Viktorovich Bolotnikov
  • Publication number: 20150144960
    Abstract: The subject matter disclosed herein relates to metal-oxide-semiconductor (MOS) devices, such as silicon carbide (SiC) power devices (e.g., MOSFETs, IGBTs, etc.) In an embodiment, a semiconductor device includes a gate oxide layer disposed on top of a semiconductor layer. The semiconductor device also includes a gate electrode having a tapered sidewall. Further, the gate electrode includes a polysilicon layer disposed on top of the gate oxide layer and a metal silicide layer disposed on top of the polysilicon layer.
    Type: Application
    Filed: November 27, 2013
    Publication date: May 28, 2015
    Applicant: General Electric Company
    Inventors: Richard Joseph Saia, Stephen Daley Arthur, Zachary Matthew Stum, Roger Raymond Kovalec, Gregory Keith Dudoff
  • Publication number: 20150115284
    Abstract: A semiconductor device includes a substrate including silicon carbide; a drift layer disposed over the substrate including a drift region doped with a first dopant and conductivity type; and a second region, doped with a second dopant and conductivity type, adjacent to the drift region and proximal to a surface of the drift layer. The semiconductor device further includes a junction termination extension adjacent to the second region with a width and discrete regions separated in a first and second direction doped with varying concentrations of the second dopant type, and an effective doping profile of the second conductivity type of functional form that generally decreases away from the edge of the primary blocking junction. The width is less than or equal to a multiple of five times the width of the one-dimensional depletion width, and the charge tolerance of the semiconductor device is greater than 1.0×1013 per cm2.
    Type: Application
    Filed: May 15, 2013
    Publication date: April 30, 2015
    Inventors: Stephen Daley Arthur, Alexander Viktorovich Bolotnikov, Peter Almern Losee, Kevin Sean Matocha, Richard Joseph Saia, Zachary Matthew Stum, Ljubisa Dragoljub Stevanovic, Kuna Venkat Satya Rama Kishore, James William Kretchmer
  • Patent number: 9006027
    Abstract: An electrical device includes a blocking layer disposed on top of a substrate layer, wherein the blocking layer and the substrate layer each are wide bandgap semiconductors, and the blocking layer and the substrate layer form a buried junction in the electrical device. The device comprises a termination feature disposed at a surface of the blocking layer and a filled trench disposed proximate to the termination feature. The filled trench extends through the blocking layer to reach the substrate layer and is configured to direct an electrical potential associated with the buried junction toward the termination feature disposed near the surface of the blocking layer to terminate the buried junction.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: April 14, 2015
    Assignee: General Electric Company
    Inventors: Zachary Matthew Stum, Ahmed Elasser, Stephen Daley Arthur, Stanislav I. Soloviev, Peter Almern Losee
  • Publication number: 20140361315
    Abstract: A semiconductor device according to one embodiment having a first region comprising a first dopant type, a second region adjacent the first region haivng a second dopant type and a channel region. There is a third region segregated from the channel region having a second dopant type, wherein the third region substantially coincides with the second region.
    Type: Application
    Filed: August 25, 2014
    Publication date: December 11, 2014
    Inventors: Zachary Matthew Stum, Stephen Daley Arthur, Kevin Sean Matocha, Peter Almern Losee
  • Patent number: 8815721
    Abstract: A method comprising, introducing a dopant type into a semiconductor layer to define a well region of the semiconductor layer, the well region comprising a channel region, and introducing a dopant type into the well region to define a multiple implant region substantially coinciding with the well region but excluding the channel region.
    Type: Grant
    Filed: December 17, 2010
    Date of Patent: August 26, 2014
    Assignee: General Electric Company
    Inventors: Zachary Matthew Stum, Stephen Daley Arthur, Kevin Sean Matocha, Peter Almern Losee
  • Publication number: 20140167068
    Abstract: A silicon carbide device is presented that includes a gate electrode disposed over a portion of a silicon carbide substrate as well as a dielectric film disposed over the gate electrode. The device has a contact region disposed near the gate electrode and has a layer disposed over the dielectric film and over the contact region. The layer includes nickel in portions disposed over the dielectric film and includes nickel silicide in portions disposed over the contact region. The nickel silicide layer is configured to provide an ohmic contact to the contact region of the silicon carbide device.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Zachary Matthew Stum, Reza Ghandi
  • Publication number: 20140070229
    Abstract: An electrical device includes a blocking layer disposed on top of a substrate layer, wherein the blocking layer and the substrate layer each are wide bandgap semiconductors, and the blocking layer and the substrate layer form a buried junction in the electrical device. The device comprises a termination feature disposed at a surface of the blocking layer and a filled trench disposed proximate to the termination feature. The filled trench extends through the blocking layer to reach the substrate layer and is configured to direct an electrical potential associated with the buried junction toward the termination feature disposed near the surface of the blocking layer to terminate the buried junction.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 13, 2014
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Zachary Matthew Stum, Ahmed Elasser, Stephen Daley Arthur, Stanislav I. Soloviev, Peter Almern Losee
  • Publication number: 20130334612
    Abstract: An integrated circuit includes a plurality of transistors. Each transistor is associated with a corresponding body terminal. At least one transistor is reverse biased at a first voltage level, and at least one other transistor is reverse biased at a second voltage level that is different from the first voltage level. Each body terminal is electrically isolated from every other body terminal via an isolation barrier. A transistor that is reverse biased at the first voltage level is electrically connected to a transistor that is reverse biased at the second voltage level, such that the electrically connected transistors operate to interact with each other while the respective body voltage levels are different from each other and are changing independently of each other during operation of the integrated circuit.
    Type: Application
    Filed: August 13, 2013
    Publication date: December 19, 2013
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Cheng-Po Chen, Emad Andarawis Andarawis, Vinayak Tilak, Zachary Matthew Stum
  • Patent number: 8507986
    Abstract: In one embodiment, the invention comprises a MOSFET comprising individual MOSFET cells. Each cell comprises a U-shaped well (P type) and two parallel sources (N type) formed within the well. A Number of source rungs (doped N) connect sources at multiple locations. Regions between two rungs comprise a body (P type). These features are formed on an N-type epitaxial layer, which is formed on an N-type substrate. A contact extends across and contacts a number of source rungs and bodies. Gate oxide and a gate contact overlie a leg of a first well and a leg of a second adjacent well, inverting the conductivity responsive to a gate voltage. A MOSFET comprises a plurality of these cells to attain a desired low channel resistance. The cell regions are formed using self-alignment techniques at several states of the fabrication process.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: August 13, 2013
    Assignee: General Electric Company
    Inventors: Stephen Daley Arthur, Kevin Sean Matocha, Peter Micah Sandvik, Zachary Matthew Stum, Peter Almren Losee, James Jay McMahon
  • Patent number: 8377812
    Abstract: The present invention provides a method of fabricating a metal oxide semiconductor field effect transistor. The method includes the steps of forming a source region on a silicon carbide layer and annealing the source region. A gate oxide layer is formed on the source region and the silicon carbide layer. The method further includes providing a gate electrode on the gate oxide layer and disposing a dielectric layer on the gate electrode and the gate oxide layer. The method further includes etching a portion of the dielectric layer and a portion of the gate oxide layer to form sidewalls on the gate electrode. A metal layer is disposed on the gate electrode, the sidewalls and the source region. The method further includes forming a gate contact and a source contact by subjecting the metal layer to a temperature of at least about 800° C. The gate contact and the source contact comprise a metal silicide. The distance between the gate contact and the source contact is less than about 0.6 ?m.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: February 19, 2013
    Assignee: General Electric Company
    Inventors: Kevin Sean Matocha, Gregory Keith Dudoff, William Gregg Hawkins, Zachary Matthew Stum, Stephen Daley Arthur, Dale Marius Brown
  • Publication number: 20120153362
    Abstract: A method comprising, introducing a dopant type into a semiconductor layer to define a well region of the semiconductor layer, the well region comprising a channel region, and introducing a dopant type into the well region to define a multiple implant region substantially coinciding with the well region but excluding the channel region.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 21, 2012
    Applicant: GENERAL ELECTRIC COMPANY
    Inventors: Zachary Matthew Stum, Stephen Daley Arthur, Kevin Sean Matocha, Peter Almern Losee
  • Patent number: 7829402
    Abstract: A MOSFET device and a method for fabricating MOSFET devices are disclosed. The method includes providing a semiconductor device structure including a semiconductor device layer of a first conductivity type, and ion implanting a well structure of a second conductivity type in the semiconductor device layer, where the ion implanting includes providing a dopant concentration profile in a single mask implant sequence.
    Type: Grant
    Filed: February 10, 2009
    Date of Patent: November 9, 2010
    Assignee: General Electric Company
    Inventors: Kevin Sean Matocha, Stephen Daley Arthur, Ramakrishna Rao, Peter Almern Losee, Zachary Matthew Stum
  • Patent number: 7807556
    Abstract: A method for doping impurities into a device layer includes providing a carbonized dopant layer including one or more dopant impurities over a device layer and heat treating the carbonized dopant layer to thermally diffuse the dopant impurities into the device layer.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: October 5, 2010
    Assignee: General Electric Company
    Inventors: Greg Thomas Dunne, Jesse Berkley Tucker, Stanislav Ivanovich Soloviev, Zachary Matthew Stum
  • Patent number: 7781312
    Abstract: A method for fabricating a SiC MOSFET is disclosed. The method includes growing a SiC epilayer over a substrate, planarizing the SiC epilayer to provide a planarized SiC epilayer, and forming a gate dielectric layer in contact with the planarized epilayer.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: August 24, 2010
    Assignee: General Electric Company
    Inventors: Kevin Sean Matocha, Vinayak Tilak, Stephen Daley Arthur, Zachary Matthew Stum