Patents by Inventor Zack S. Waters
Zack S. Waters has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11960405Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.Type: GrantFiled: December 30, 2022Date of Patent: April 16, 2024Assignee: Intel CorporationInventors: Zack S. Waters, Travis Schluessler, Michael Apodaca, Ankur Shah
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Publication number: 20230244609Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.Type: ApplicationFiled: December 30, 2022Publication date: August 3, 2023Applicant: Intel CorporationInventors: ZACK S. WATERS, TRAVIS SCHLUESSLER, MICHAEL APODACA, ANKUR SHAH
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Patent number: 11580027Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.Type: GrantFiled: February 26, 2020Date of Patent: February 14, 2023Assignee: Intel CorporationInventors: Zack S. Waters, Travis Schluessler, Michael Apodaca, Ankur Shah
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Publication number: 20210263853Abstract: Graphics processors for implementing multi-tile memory management are disclosed. In one embodiment, a graphics processor includes a first graphics device having a local memory, a second graphics device having a local memory, and a graphics driver to provide a single virtual allocation with a common virtual address range to mirror a resource to each local memory of the first and second graphics devices.Type: ApplicationFiled: February 26, 2020Publication date: August 26, 2021Applicant: Intel CorporationInventors: ZACK S. WATERS, TRAVIS SCHLUESSLER, MICHAEL APODACA, ANKUR SHAH
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Publication number: 20200151847Abstract: Examples are described here that can be used to allocate primitive visibility determination to a particular graphics processor or group of graphics processors. The particular graphics processor or group of graphics processors can determine which region of a frame a primitive is visible in. For example, a frame can include multiple regions. One or more graphics processors can be assigned to a particular region to handle rasterization of primitives that are visible within the particular region. The one or more graphics processors assigned to a particular region can be free to perform other tasks and perform rasterization and additional tasks solely for the visible primitives.Type: ApplicationFiled: November 13, 2018Publication date: May 14, 2020Inventors: Travis SCHLUESSLER, Zack S. WATERS, Michael APODACA
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Patent number: 10026150Abstract: Methods, apparatus and articles of manufacture for graphics processing of a vertex buffer using a relative index buffer are disclosed. Example methods to process a vertex buffer disclosed herein include accessing a first relative index stored in a relative index buffer, the first relative index specifying an offset from a current index selecting a first entry of the vertex buffer. Such disclosed example methods also include, in response to the first relative index being a nonzero value, processing data associated with a second entry of the vertex buffer to determine a rasterizer output associated with the first entry of the vertex buffer, the second entry of the vertex buffer being selected using the current index offset by the first relative index.Type: GrantFiled: December 21, 2016Date of Patent: July 17, 2018Assignee: INTEL CORPORATIONInventors: Jacob N. Smith, Jason M. Surprise, Zack S. Waters
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Patent number: 9824413Abstract: Methods and apparatus relating to sort-free threading model for a multi-threaded graphics pipeline are described. In an embodiment, draw requests, corresponding to one or more primitives in an image, are stored in entries of a queue (e.g., in the order received). Each entry remains locked until both a front-end and a back-end of a graphics pipeline have completed one or more operations associated with the draw request. Other embodiments are also disclosed and claimed.Type: GrantFiled: November 15, 2014Date of Patent: November 21, 2017Assignee: Intel CorporationInventors: Jason M. Surprise, Zack S. Waters
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Publication number: 20170169538Abstract: Methods, apparatus and articles of manufacture for graphics processing of a vertex buffer using a relative index buffer are disclosed. Example methods to process a vertex buffer disclosed herein include accessing a first relative index stored in a relative index buffer, the first relative index specifying an offset from a current index selecting a first entry of the vertex buffer. Such disclosed example methods also include, in response to the first relative index being a nonzero value, processing data associated with a second entry of the vertex buffer to determine a rasterizer output associated with the first entry of the vertex buffer, the second entry of the vertex buffer being selected using the current index offset by the first relative index.Type: ApplicationFiled: December 21, 2016Publication date: June 15, 2017Inventors: Jacob N. Smith, Jason M. Surprise, Zack S. Waters
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Patent number: 9536278Abstract: Methods, apparatus and articles of manufacture for graphics processing of a vertex buffer using a relative index buffer are disclosed. Example methods to process a vertex buffer disclosed herein include accessing a first relative index stored in a relative index buffer, the first relative index specifying an offset from a current index selecting a first entry of the vertex buffer. Such disclosed example methods also include, in response to the first relative index being a nonzero value, processing data associated with a second entry of the vertex buffer to determine a rasterizer output associated with the first entry of the vertex buffer, the second entry of the vertex buffer being selected using the current index offset by the first relative index.Type: GrantFiled: November 27, 2013Date of Patent: January 3, 2017Assignee: Intel CorporationInventors: Jacob N. Smith, Jason M. Surprise, Zack S. Waters
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Publication number: 20160140684Abstract: Methods and apparatus relating to sort-free threading model for a multi-threaded graphics pipeline are described. In an embodiment, draw requests, corresponding to one or more primitives in an image, are stored in entries of a queue (e.g., in the order received). Each entry remains locked until both a front-end and a back-end of a graphics pipeline have completed one or more operations associated with the draw request. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: November 15, 2014Publication date: May 19, 2016Applicant: Intel CorporationInventors: JASON M. SURPRISE, ZACK S. WATERS
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Publication number: 20150145880Abstract: Methods, apparatus and articles of manufacture for graphics processing of a vertex buffer using a relative index buffer are disclosed. Example methods to process a vertex buffer disclosed herein include accessing a first relative index stored in a relative index buffer, the first relative index specifying an offset from a current index selecting a first entry of the vertex buffer. Such disclosed example methods also include, in response to the first relative index being a nonzero value, processing data associated with a second entry of the vertex buffer to determine a rasterizer output associated with the first entry of the vertex buffer, the second entry of the vertex buffer being selected using the current index offset by the first relative index.Type: ApplicationFiled: November 27, 2013Publication date: May 28, 2015Inventors: Jacob N. Smith, Jason M. Surprise, Zack S. Waters
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Patent number: 7945416Abstract: A software or hardware test system and method repeatedly obtains testing status of a plurality of test units in a group while the test units are testing hardware or software being executed on the test units. The system and method provides for display of the current testing status of the plurality of units of the group while the plurality of test units is performing software testing. In another embodiment, a test system and method compiles heuristic data for a plurality of test units that are assigned to one or more groups of test units. The heuristic data may include, for example, data representing a frequency of use on a per-test unit basis over a period of time, and other heuristic data. The test system and method evaluates job queue sizes on a per-group basis to determine whether there are under-utilized test units in the group and determines on a per-group of test unit basis whether a first group allows for dynamic reassignment of a test unit in the group based on at least the compiled heuristic data.Type: GrantFiled: April 12, 2006Date of Patent: May 17, 2011Assignee: ATI Technologies, ULCInventors: Nicholas A. Haemel, Zack S. Waters