Abstract: The multiple modem apparatus has a number of analog front ends that feed analog signals to and receive analog signals from a modem controller circuit. The modem controller circuit has a codec function for sampling, quantizing, and digitizing the received analog signals. The codec additionally creates an analog signal from digitized signals received from the other side of the modem apparatus. A digital signal processing function provides digital processing of digital signals. An Ethernet device converts digital signals from the modem controller circuit to the Ethernet format and Ethernet signals going to the modem controller circuit are converted from the Ethernet format to digital data. A multiple modem apparatus controller controls the operation of the apparatus while providing synchronization of the multiple analog front ends and routing of data.

Abstract: A method and apparatus for generating a stable high frequency clock from a low frequency reference signal performs most of its operations in a digital environment. The method and apparatus reduce complexity and cost by reducing the number of digital to analog and analog to digital conversions and eliminating synchronous counters.

Abstract: A digital to analog converter is provided. The converter includes a multi-bit counter, a first and a second plurality of logic gates coupled to the multi-bit counter, a digital input selectively coupled to the first and second plurality of logic gates. . The converter further includes a first AND gate coupled to an output of the first plurality of logic gates and a second AND gate coupled to an output of the second plurality of logic gates. In addition, the converter includes a clock coupled to an input of the first and second AND gates and an input of the multi-bit counter and a filter coupled to an output of the first and second AND gates, wherein the filter includes an output for an analog signal based on the digital input.

Abstract: A digital to analog converter is provided. The converter includes a multi-bit counter, a first and a second plurality of logic gates coupled to the multi-bit counter, a digital input selectively coupled to the first and second plurality of logic gates. The converter further includes a first AND gate coupled to an output of the first plurality of logic gates and a second AND gate coupled to an output of the second plurality of logic gates. In addition, the converter includes a clock coupled to an input of the first and second AND gates and an input of the multi-bit counter and a filter coupled to an output of the first and second AND gates, wherein the filter includes an output for an analog signal based on the digital input.