Patents by Inventor Zafer Kutlu

Zafer Kutlu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120018901
    Abstract: A method of manufacturing a flip-chip package and a flip-chip package manufactured by such method. In one embodiment, the method includes: (1) mounting a die to a first die, (2) encapsulating the second die with a molding compound and (3) selectively ablating the molding compound based on an expected heat generation of portions of the second die to reduce a thickness of the molding compound proximate the portions.
    Type: Application
    Filed: July 21, 2010
    Publication date: January 26, 2012
    Applicant: LSI Corporation
    Inventors: Patrick Variot, Qwai Low, Zafer Kutlu
  • Patent number: 7479703
    Abstract: An integrated circuit package includes an integrated circuit die having a circuit surface and a back surface opposite the circuit surface. A layer of ductile material is deposited on the back surface of the integrated circuit die.
    Type: Grant
    Filed: July 2, 2007
    Date of Patent: January 20, 2009
    Assignee: LSI Logic Corporation
    Inventor: Zafer Kutlu
  • Publication number: 20090008767
    Abstract: An integrated circuit package includes an integrated circuit die having a circuit surface and a back surface opposite the circuit surface. A layer of ductile material is deposited on the back surface of the integrated circuit die.
    Type: Application
    Filed: July 2, 2007
    Publication date: January 8, 2009
    Inventor: ZAFER KUTLU
  • Publication number: 20080290502
    Abstract: An integrated circuit die includes a circuit surface and a back surface opposite the circuit surface. An underbump metallurgy is formed on a back surface. A layer of solder is formed on the underbump metallurgy.
    Type: Application
    Filed: May 25, 2007
    Publication date: November 27, 2008
    Inventor: Zafer Kutlu
  • Patent number: 7354790
    Abstract: A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: April 8, 2008
    Assignee: LSI Logic Corporation
    Inventors: Parthasarathy Rajagopalan, Zafer Kutlu, Emery O. Sugasawara, Charles E. Vonderach, Dilip P. Vijay, Yogendra Ranade, Jeff Hall, Dwight Manning
  • Patent number: 7345245
    Abstract: A semiconductor package for a die with improved thermal cycling reliability. A first layer of the package provides ball pads dispersed throughout. A second layer of the package provides signal traces. A high stress area associated with the corner of the dies is defined. Preferably the high stress area is defined as two ball pitches away from the corner of the die. Signal traces are routed away from the high stress area and in particular signal traces are routed away from the ball pads associated with the high stress to eliminate the cracks in the routed traces.
    Type: Grant
    Filed: October 8, 2003
    Date of Patent: March 18, 2008
    Assignee: LSI Logic Corporation
    Inventors: Anand Govind, Zafer Kutlu, Farshad Ghahghahi
  • Patent number: 7190082
    Abstract: An underfill includes a base material and a filler material added to the base material wherein the filler material constitutes a selected percentage by weight of the underfill to provide an optimum balance between interfacial die stress and solder bump strain for next generation, Cu, low-K silicon technology.
    Type: Grant
    Filed: March 24, 2003
    Date of Patent: March 13, 2007
    Assignee: LSI Logic Corporation
    Inventors: Kumar Nagarajan, Zafer Kutlu
  • Publication number: 20060267615
    Abstract: A zero automated electrical testing (ATE) interposer daughter card (IDC) is provided for use in a test apparatus for ATE. Embodiments of the IDC include a first side having a first set of pads for mounting I/O's of a test package; and a second side having a second set of pads coupled to the first set of pads for replicating the first set of pads, wherein the second set of pads is located in area of the interposer card horizontally offset from the first set of pads, such that ATE measurements are obtained by removably inserting only a portion of the interposer card containing the second set of pads into an ATE test socket.
    Type: Application
    Filed: May 27, 2005
    Publication date: November 30, 2006
    Inventors: Carlo Grilletto, Zafer Kutlu
  • Publication number: 20060160269
    Abstract: A method and apparatus for avoiding dicing chip-outs in integrated circuit die comprises: (a) providing a wafer for forming a plurality of integrated circuit die thereon; (b) forming the plurality of integrated circuit die on the wafer; and (c) forming a saw street between the integrated circuit die on the wafer to relieve cutting stress in the wafer when the integrated circuit die are separated by a dicing saw.
    Type: Application
    Filed: May 18, 2005
    Publication date: July 20, 2006
    Inventors: Parthasarathy Rajagopalan, Zafer Kutlu, Emery Sugasawara, Charles Vonderach, Dilip Vijay, Yogendra Ranade, Jeff Hall, Dwight Manning
  • Publication number: 20050077081
    Abstract: A semiconductor package for a die with improved thermal cycling reliability. A first layer of the package provides ball pads dispersed throughout. A second layer of the package provides signal traces. A high stress area associated with the corner of the dies is defined. Preferably the high stress area is defined as two ball pitches away from the corner of the die. Signal traces are routed away from the high stress area and in particular signal traces are routed away from the ball pads associated with the high stress to eliminate the cracks in the routed traces.
    Type: Application
    Filed: October 8, 2003
    Publication date: April 14, 2005
    Inventors: Anand Govind, Zafer Kutlu, Farshad Ghahghahi
  • Patent number: 6806119
    Abstract: A flip chip ball grid array package includes a thin die having a die thickness reduced from a wafer thickness to reduce mismatch of a coefficient of thermal expansion between the thin die and a substrate; a plurality of thin film layers formed on the thin die wherein each of the plurality of thin film layers has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of the substrate; and a plurality of wafer bumps formed on the thin die for making electrical contact between the thin die and the substrate.
    Type: Grant
    Filed: July 30, 2003
    Date of Patent: October 19, 2004
    Assignee: LSI Logic Corporation
    Inventors: Kumar Nagarajan, Zafer Kutlu, Shirish Shah
  • Publication number: 20040188862
    Abstract: An underfill includes a base material and a filler material added to the base material wherein the filler material constitutes a selected percentage by weight of the underfill to provide an optimum balance between interfacial die stress and solder bump strain for next generation, Cu, low-K silicon technology.
    Type: Application
    Filed: March 24, 2003
    Publication date: September 30, 2004
    Inventors: Kumar Nagarajan, Zafer Kutlu
  • Publication number: 20040121519
    Abstract: A flip chip ball grid array package includes a thin die having a die thickness reduced from a wafer thickness to reduce mismatch of a coefficient of thermal expansion between the thin die and a substrate; a plurality of thin film layers formed on the thin die wherein each of the plurality of thin film layers has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of the substrate; and a plurality of wafer bumps formed on the thin die for making electrical contact between the thin die and the substrate.
    Type: Application
    Filed: July 30, 2003
    Publication date: June 24, 2004
    Inventors: Kumar Nagarajan, Zafer Kutlu, Shirish Shah
  • Patent number: 6639321
    Abstract: A flip chip ball grid array package includes a thin die having a die thickness reduced from a wafer thickness to reduce mismatch of a coefficient of thermal expansion between the thin die and a substrate; a plurality of thin film layers formed on the thin die wherein each of the plurality of thin film layers has a coefficient of thermal expansion that is greater than that of the thin die and is less than that of the substrate; and a plurality of wafer bumps formed on the thin die for making electrical contact between the thin die and the substrate.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: October 28, 2003
    Assignee: LSI Logic Corporation
    Inventors: Kumar Nagarajan, Zafer Kutlu, Shirish Shah
  • Patent number: 6534968
    Abstract: An apparatus for detecting failures in electrical connections between an integrated circuit package substrate and a circuit board. The substrate has substrate electrical contacts that are electrically connected one to another in first sets in a first region of the substrate. The circuit board has circuit board electrical contacts that are electrically connected one to another in second sets in a second region of the circuit board. The substrate electrical contacts align with and make electrical contact with the circuit board electrical contacts. The first region of the substrate aligns with the second region of the circuit board when the substrate electrical contacts make electrical contact with the circuit board electrical contacts. The first sets of substrate electrical contacts form chains of electrical contacts with the second sets of circuit board electrical contacts. The chains of electrical contacts loop back and forth electrically between the substrate and the circuit board.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: March 18, 2003
    Assignee: LSI Logic Corporation
    Inventors: Leah M. Miller, Anand Govind, Zafer Kutlu, Chao-Wen Chung, Aritharan Thurairajaratnam