Patents by Inventor Zafer S. Kutlu
Zafer S. Kutlu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11410977Abstract: An electronic module can include a first integrated device package comprising a first substrate and an electronic component mounted to the first substrate. A first vertical interconnect can be mounted to and electrically connected to the first substrate. The first vertical interconnect can extend outwardly from the first substrate. The electronic module can include a second integrated device package comprising a second substrate and a second vertical interconnect having a first end mounted to and electrically connected to the second substrate. The second vertical interconnect can have a second end electrically connected to the first vertical interconnect. The first and second vertical interconnects can be disposed between the first and second substrates.Type: GrantFiled: November 12, 2019Date of Patent: August 9, 2022Assignee: Analog Devices International Unlimited CompanyInventors: John D. Brazzle, Frederick E. Beville, Yucheng Ying, Zafer S. Kutlu
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Publication number: 20200152614Abstract: An electronic module can include a first integrated device package comprising a first substrate and an electronic component mounted to the first substrate. A first vertical interconnect can be mounted to and electrically connected to the first substrate. The first vertical interconnect can extend outwardly from the first substrate. The electronic module can include a second integrated device package comprising a second substrate and a second vertical interconnect having a first end mounted to and electrically connected to the second substrate. The second vertical interconnect can have a second end electrically connected to the first vertical interconnect. The first and second vertical interconnects can be disposed between the first and second substrates.Type: ApplicationFiled: November 12, 2019Publication date: May 14, 2020Inventors: John D. Brazzle, Frederick E. Beville, Yucheng Ying, Zafer S. Kutlu
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Patent number: 7968999Abstract: A method of grounding a heat spreader/stiffener to a flip chip package comprising the steps of attaching an adhesive film to a substrate and attaching a stiffener to the adhesive film. The adhesive film may have a number of first holes corresponding with a number of grounding pads on the substrate. The grounding pads may be configured to provide electrical grounding. The stiffener may have a number of second holes corresponding with the number of first holes of the adhesive film and number the grounding pads of the substrate. The grounding pads are generally exposed through the first and the second holes.Type: GrantFiled: February 28, 2008Date of Patent: June 28, 2011Assignee: LSI CorporationInventors: Zeki Z. Celik, Zafer S. Kutlu, Vishal Shah
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Publication number: 20090218680Abstract: A method of grounding a heat spreader/stiffener to a flip chip package comprising the steps of attaching an adhesive film to a substrate and attaching a stiffener to the adhesive film. The adhesive film may have a number of first holes corresponding with a number of grounding pads on the substrate. The grounding pads may be configured to provide electrical grounding. The stiffener may have a number of second holes corresponding with the number of first holes of the adhesive film and number the grounding pads of the substrate. The grounding pads are generally exposed through the first and the second holes.Type: ApplicationFiled: February 28, 2008Publication date: September 3, 2009Inventors: Zeki Z. Celik, Zafer S. Kutlu, Vishal Shah
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Patent number: 7528616Abstract: A zero automated electrical testing (ATE) interposer daughter card (IDC) is provided for use in a test apparatus for ATE. Embodiments of the IDC include a first side having a first set of pads for mounting I/O's of a test package; and a second side having a second set of pads coupled to the first set of pads for replicating the first set of pads, wherein the second set of pads is located in area of the interposer card horizontally offset from the first set of pads, such that ATE measurements are obtained by removably inserting only a portion of the interposer card containing the second set of pads into an ATE test socket.Type: GrantFiled: May 27, 2005Date of Patent: May 5, 2009Assignee: LSI CorporationInventors: Carlo Grilletto, Zafer S. Kutlu
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Patent number: 7096748Abstract: An apparatus generally having a circuit board and a first strain gauge is disclosed. The circuit board may have a plurality of insulating layers. The first strain gauge may be disposed between two of the insulating layers.Type: GrantFiled: July 28, 2004Date of Patent: August 29, 2006Assignee: LSI Logic CorporationInventor: Zafer S. Kutlu
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Publication number: 20060021453Abstract: An apparatus generally having a circuit board and a first strain gauge is disclosed. The circuit board may have a plurality of insulating layers. The first strain gauge may be disposed between two of the insulating layers.Type: ApplicationFiled: July 28, 2004Publication date: February 2, 2006Inventor: Zafer S. Kutlu
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Publication number: 20040070073Abstract: A package substrate having pads for receiving an integrated circuit, where the improvement is the pads having a height of between about two mils and about three mils. In this manner, additional structures such as solder on the pads do not need to be added, and coined, in order to ensure a minimum gap between the package substrate and the monolithic integrated circuit. The pads may be formed of at least one of copper, nickel, and gold. Also described is a packaged integrated circuit having a package substrate with pads for receiving a monolithic integrated circuit, where the improvement is the pads having a height of between about two mils and about three mils. The monolithic integrated circuit is attached to the pads with solder bumps.Type: ApplicationFiled: October 15, 2002Publication date: April 15, 2004Inventors: Shirish Shah, Zafer S. Kutlu, Kumar Nagarajan
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Patent number: 6673708Abstract: An integrated circuit structure and a method for packaging an integrated circuit are described. The integrated structure includes an integrated circuit that is inverted and solder bump mounted to a substrate. An underfill is used to encapsulate the solder bumps and form a rigid support layer between the integrated circuit and the substrate. A heatspreader, which has larger planar dimensions than the integrated circuit, is centrally attached to an upper surface of the integrated circuit with a thermally conductive material. Lateral portions of the heatspreader extending beyond the edges of the integrated circuit are attached to the substrate and sides of the integrated circuit by a thermally conductive underfill material. The thermally conductive underfill material thus employed, among other things, provides a robust mechanical support to the heatspreader and integrated circuit structure and eliminates the need for additional support structures such as conventional stiffener rings.Type: GrantFiled: March 25, 2003Date of Patent: January 6, 2004Assignee: LSI Logic CorporationInventors: Ivor G. Barber, Zafer S. Kutlu
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Patent number: 6590292Abstract: An integrated circuit structure and a method for packaging an integrated circuit are described. The integrated structure includes an integrated circuit that is inverted and solder bump mounted to a substrate. An underfill is used to encapsulate the solder bumps and form a rigid support layer between the integrated circuit and the substrate. A heatspreader, which has larger planar dimensions than the integrated circuit, is centrally attached to an upper surface of the integrated circuit with a thermally conductive material. Lateral portions of the heatspreader extending beyond the edges of the integrated circuit are attached to the substrate and sides of the integrated circuit by a thermally conductive underfill material. The thermally conductive underfill material thus employed, among other things, provides a robust mechanical support to the heatspreader and integrated circuit structure and eliminates the need for additional support structures such as conventional stiffener rings.Type: GrantFiled: June 1, 2001Date of Patent: July 8, 2003Assignee: LSI Logic CorporationInventors: Ivor G. Barber, Zafer S. Kutlu
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Patent number: 6472762Abstract: A flipchip packaged integrated circuit comprising a substrate, a die and a heatspreader. The die may be configured to electrically attach to the substrate. The heat spreader may be rigidly attached to the die. The die and the heatspreader may have a combined coefficient of thermal expansion when attached. The heatspreader may be configured to match the combined coefficient of thermal expansion and a coefficient of thermal expansion of the substrate.Type: GrantFiled: August 31, 2001Date of Patent: October 29, 2002Assignee: LSI Logic CorporationInventor: Zafer S. Kutlu
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Patent number: 6465338Abstract: Disclosed is a method of planarizing an array of plastically-deformable electrical contacts on an integrated circuit. An integrated circuit is placed on a plate with an array of plastically-deformable electrical contacts substantially parallel to and facing the plate, thereby creating an assembly. The integrated circuit is placed above the plate such that the weight of the integrated circuit bears down on the array of plastically-deformable electrical contacts. The assembly is then heated sufficiently to cause individual ones of the plastically-deformable electrical contacts to locally soften but not to cause said individual ones of the electrical contacts to liquefy throughout their volumes. The weight of the integrated circuit applies a force to the softened plastically-deformable electrical contacts, thereby resulting in their planarization.Type: GrantFiled: July 10, 2000Date of Patent: October 15, 2002Assignee: LSI Logic CorporationInventors: Sarathy Rajagopalan, Kishor V. Desai, Zafer S. Kutlu
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Patent number: 6114761Abstract: A thermally-enhanced flip chip integrated circuit (IC) package has a package substrate to which an IC die is bonded. A thermally-conductive heatspreader, having planar dimensions larger than the IC die, is thermally bonded at or near its center to an upper surface of the IC die. A plurality of cooling extensions are formed that protrude from a lower surface (the surface closest to the package substrate) of the heatspreader so as to create passageways through which cooling air may flow. In one embodiment, the cooling extensions are parallel fins that protrude transversely from the lower surface of the heatspreader, thereby forming U-shaped channels. In another embodiment, the cooling extensions are an array of fin pins that protrude transversely from the lower surface of the heatspreader.Type: GrantFiled: January 20, 1998Date of Patent: September 5, 2000Assignee: LSI Logic CorporationInventors: Atila Mertol, Zeki Z. Celik, Farshad Ghahghahi, Zafer S. Kutlu
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Patent number: 6111313Abstract: A system and method are presented for forming a grid array device package around an integrated circuit (i.e., chip). The device package includes a substrate, a stiffener, a heat spreader, and an optional heat sink. The chip includes multiple I/O pads arranged upon an underside surface. The substrate includes a first set of bonding pads on an upper surface configured to vertically align with the I/O pads. The chip is connected to the first set of bonding pads using the C4 method. The stiffener, a rigid member able to retain its shape during C4 heating, may be attached to the upper surface of the substrate prior to the C4 process, helping the substrate maintain its planarity during and after the C4 process. The stiffener has an opening dimensioned to receive the chip and exposing the first set of bonding pads. Following the C4 process, a first space between the underside surface of the chip and the upper surface of the substrate is filled with an underfill material.Type: GrantFiled: January 12, 1998Date of Patent: August 29, 2000Assignee: LSI Logic CorporationInventor: Zafer S. Kutlu