Patents by Inventor Zahid Ahsanullah

Zahid Ahsanullah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7417481
    Abstract: A circuit includes an input terminal, an output terminal and a latch. The input terminal receives an input signal. The latch is programmable with a value. The latch communicates the input signal to the output terminal in response to the circuit not being in a sleep mode and in response to the circuit being in the sleep mode, furnishes a second signal to the output terminal indicative of the value.
    Type: Grant
    Filed: October 21, 2004
    Date of Patent: August 26, 2008
    Assignee: Intel Corporation
    Inventors: Zahid Ahsanullah, Michael Longwell, James R. Feddeler
  • Patent number: 7254728
    Abstract: Power saving method is achieved by weakly holding a signal line in its last in time state, which is responsive to and may be overcome by the state of an external signal. During sleep mode, the weakly held signal line state tracks and holds the external signal using alternatively a controllable weak pull-up or pull-down device, such that weakly held state may be driven to a different state by the external driving signal with slight power consumption. When sleep mode is off, the keeper function is disabled and the signal line maybe driven alternatively internally or externally depending upon the state of an enable line.
    Type: Grant
    Filed: March 21, 2006
    Date of Patent: August 7, 2007
    Assignee: Intel Corporation
    Inventors: Gregory Rose, James R. Feddeler, Zahid Ahsanullah
  • Publication number: 20060179336
    Abstract: Power saving method is achieved by weakly holding a signal line in its last in time state, which is responsive to and may be overcome by the state of an external signal. During sleep mode, the weakly held signal line state tracks and holds the external signal using alternatively a controllable weak pull-up or pull-down device, such that weakly held state may be driven to a different state by the external driving signal with slight power consumption. When sleep mode is off, the keeper function is disabled and the signal line maybe driven alternatively internally or externally depending upon the state of an enable line.
    Type: Application
    Filed: March 21, 2006
    Publication date: August 10, 2006
    Inventors: Gregory Rose, James Feddeler, Zahid Ahsanullah
  • Patent number: 7058827
    Abstract: Power saving method is achieved by weakly holding a signal line in its last in time state, which is responsive to and may be overcome by the state of an external signal. During sleep mode, the weakly held signal line state tracks and holds the external signal using alternatively a controllable weak pull-up or pull-down device, such that weakly held state may be driven to a different state by the external driving signal with slight power consumption. When sleep mode is off, the keeper function is disabled and the signal line maybe driven alternatively internally or externally depending upon the state of an enable line.
    Type: Grant
    Filed: July 18, 2001
    Date of Patent: June 6, 2006
    Assignee: Intel Corporation
    Inventors: Gregory Rose, James R. Feddeler, Zahid Ahsanullah
  • Publication number: 20050083103
    Abstract: A circuit includes an input terminal, an output terminal and a latch. The input terminal receives an input signal. The latch is programmable with a value. The latch communicates the input signal to the output terminal in response to the circuit not being in a sleep mode and in response to the circuit being in the sleep mode, furnishes a second signal to the output terminal indicative of the value.
    Type: Application
    Filed: October 7, 2004
    Publication date: April 21, 2005
    Inventors: Zahid Ahsanullah, Michael Longwell, James Feddeler
  • Patent number: 6882200
    Abstract: A circuit includes an input terminal, an output terminal and a latch. The input terminal receives an input signal. The latch is programmable with a value. The latch communicates the input signal to the output terminal in response to the circuit not being in a sleep mode and in response to the circuit being in the sleep mode, furnishes a second signal to the output terminal indicative of the value.
    Type: Grant
    Filed: July 23, 2001
    Date of Patent: April 19, 2005
    Assignee: Intel Corporation
    Inventors: Zahid Ahsanullah, Michael Longwell, James R. Feddeler
  • Publication number: 20050052206
    Abstract: A circuit includes an input terminal, an output terminal and a latch. The input terminal receives an input signal. The latch is programmable with a value. The latch communicates the input signal to the output terminal in response to the circuit not being in a sleep mode and in response to the circuit being in the sleep mode, furnishes a second signal to the output terminal indicative of the value.
    Type: Application
    Filed: October 21, 2004
    Publication date: March 10, 2005
    Inventors: Zahid Ahsanullah, Michael Longwell, James Feddeler
  • Publication number: 20030028815
    Abstract: Power saving method is achieved by weakly holding a signal line in its last in time state, which is responsive to and may be overcome by the state of an external signal. During sleep mode, the weakly held signal line state tracks and holds the external signal using alternatively a controllable weak pull-up or pull-down device, such that weakly held state may be driven to a different state by the external driving signal with slight power consumption. When sleep mode is off, the keeper function is disabled and the signal line maybe driven alternatively internally or externally depending upon the state of an enable line.
    Type: Application
    Filed: July 18, 2001
    Publication date: February 6, 2003
    Inventors: Gregory Rose, James R. Feddeler, Zahid Ahsanullah
  • Publication number: 20030016062
    Abstract: A circuit includes an input terminal, an output terminal and a latch. The input terminal receives an input signal. The latch is programmable with a value. The latch communicates the input signal to the output terminal in response to the circuit not being in a sleep mode and in response to the circuit being in the sleep mode, furnishes a second signal to the output terminal indicative of the value.
    Type: Application
    Filed: July 23, 2001
    Publication date: January 23, 2003
    Inventors: Zahid Ahsanullah, Michael Longwell, James R. Feddeler
  • Publication number: 20020140453
    Abstract: A buffer driver, driving signals with edge transitions onto a transmission line is controlled to improve slew rate and glitch termination by controlling the driver to have a low impedance during a period when edge transitions are taking place, and upon cessation of edge transitions, controlling the driver to have a high impedance.
    Type: Application
    Filed: March 29, 2001
    Publication date: October 3, 2002
    Inventor: Zahid Ahsanullah
  • Patent number: 6448807
    Abstract: A buffer driver, driving signals with edge transitions onto a transmission line is controlled to improve slew rate and glitch termination by controlling the driver to have a low impedance during a period when edge transitions are taking place, and upon cessation of edge transitions, controlling the driver to have a high impedance.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: September 10, 2002
    Assignee: Intel Corporation
    Inventor: Zahid Ahsanullah
  • Patent number: 5059823
    Abstract: A supply bounce controlled output buffer circuit for producing an output signal at an output terminal pin with a significant reduction in inductive ringing includes an output stage, a first delay network (38), and a second delay network (42). The output stage includes a series-connected pull-up transistor (P1) and pull-down transistor (N1) coupled between a first power supply terminal pin and a second power supply terminal pin. The common connection of the pull-up and pull-down transistors (P1, N1) are coupled to an output terminal pin. The first delay network (38) is interconnected between the first power supply terminal pin and a control electrode of the pull-up transistor (P1) for turning off the pull-up transistor (N1) so as to slow down the rate of rise of the output signal for a portion of the time when the output terminal pin is making a low-to-high transition so as to reduce the overshoot.
    Type: Grant
    Filed: October 22, 1990
    Date of Patent: October 22, 1991
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Zahid Ahsanullah