Abstract: An inter-processor communications interface is disclosed. The interface permits the transparent movement of data from one processor to another via a memory fabric which is connected with both processors. This permits the incoming data of a first processor to be utilized by a second processor thereby freeing that processor from having to handle incoming data. Further, the second processor can handle outgoing data exclusively, freeing the first processor from having to handle outgoing data. In this way, each direction of a bi-directional dataflow may be handled by the maximum capability of a bi-directional capable processing device.

Abstract: An architecture for intercepting and processing packets from a network is disclosed. The architecture provides both stateful and stateless processing of packets in the bi-directional network flow. Further, stateless processing is provided by a parallel arrangement of network processors while stateful processing is provided by a serial arrangement of network processors. The architecture permits leveraging existing bi-directional devices to process packets in a uni-directional flow, thereby increasing the throughput of the device. The ability to share state among the stateless processor, among the stateful processors of each packet flow direction and between the stateless and stateful processors provides for dynamic adaptability and analysis of both historical and bi-directional packet activity.

Abstract: An apparatus and method for enhancing the infrastructure of a network such as the Internet is disclosed. A packet interceptor/processor apparatus is coupled with the network so as to be able to intercept and process packets flowing over the network. Further, the apparatus provides external connectivity to other devices that wish to intercept packets as well. The apparatus applies one or more rules to the intercepted packets which execute one or more functions on a dynamically specified portion of the packet and take one or more actions with the packets. The apparatus is capable of analyzing any portion of the packet including the header and payload. Actions include releasing the packet unmodified, deleting the packet, modifying the packet, logging/storing information about the packet or forwarding the packet to an external device for subsequent processing. Further, the rules may be dynamically modified by the external devices.

Abstract: A transmitting box is connected to a first electrical outlet in a building. The phase of the first electrical outlet is used as the reference phase. The transmitter box senses each of the zero-cross-overs of the reference phase and injects a data packet of the data carrier frequency at each zero-cross-over. A receiving box is connected to a second electrical outlet in the building. The second electrical outlet has an unknown phase which may be different from the reference phase. The receiver box receives each data packet and senses each phase zero-cross-over of the unknown phase. The receiver box uses the time between each reception of a data packet and each detection of an unknown phase zero-cross-over to determine the phase angle of the unknown phase relative to the reference phase.