Abstract: A method and apparatus for efficiently rasterizing graphics is provided. The method is intended to be used in combination with a frame buffer that provides fast tile-based addressing. Within this environment, frame buffer memory locations are organized into a tile hierarchy. For this hierarchy, smaller low-level tiles combine to form larger mid-level tiles. Mid-level tiles combine to form high-level tiles. The tile hierarchy may be expanded to include more levels, or collapsed to included fewer levels. A graphics primitive is rasterized by selecting an starting vertex. The low-level tile that includes the starting vertex is then rasterized. The remaining low-level tiles that are included in the same mid-level tile as the starting vertex are then rasterized. Rasterization continues with the mid-level tiles that are included in the same high-level tile as the starting vertex. These mid-level tiles are rasterized by rasterizing their component low-level tiles.

Abstract: A method and apparatus for efficiently rasterizing graphics is provided. The method is intended to be used in combination with a frame buffer that provides fast tile-based addressing. Within this environment, frame buffer memory locations are organized into a tile hierarchy. For this hierarchy, smaller low-level tiles combine to form larger mid-level tiles. Mid-level tiles combine to form high-level tiles. The tile hierarchy may be expanded to include more levels, or collapsed to included fewer levels. A graphics primitive is rasterized by selecting an starting vertex. The low-level tile that includes the starting vertex is then rasterized. The remaining low-level tiles that are included in the same mid-level tile as the starting vertex are then rasterized. Rasterization continues with the mid-level tiles that are included in the same high-level tile as the starting vertex. These mid-level tiles are rasterized by rasterizing their component low-level tiles.

Abstract: A system for prefetching information from a computer storage includes a central processing unit operable to transmit to a transfer bus a memory transfer request containing a desired memory address. The system also includes a system controller operable to receive the memory transfer request from the transfer bus and to retrieve a prefetch block of data from the computer storage in response to determining that a stream buffer local to the system controller does not contain a copy of data stored at the desired memory address. The system controller is further operable to retrieve the data from the stream buffer and communicate the data to the central processing unit in response to determining that the stream buffer contains a copy of the data stored at the desired memory address.

Abstract: A method for computing normalized minor axis distance to an ideal line for variable-width line antialiasing. The method involves performing line primitive setup by constructing a triangle from the two line vertices and a third vertex biased from a line endpoint by the line width/2. Normalized barycentric coordinates are computed for this triangle, which together can be used for primitive attribute interpolation. One of the barycentric coordinates contains the normalized minor-axis distance to the ideal line, which can be used with a slope-correct coverage table to compute coverage. Because the minor-axis distance is normalized, the coverage value is independent of line width.

Abstract: A system for performing multi-texturing operations includes a texture generation pipeline operable to receive a first graphics fragment and a second graphics fragment, to generate a first plurality of texels corresponding to the first fragment, and to generate a second plurality of texels corresponding to the second fragment. The system also includes a color pipeline coupled to the texture generation pipeline. The color pipeline is operable to receive the first and second graphics fragments and the first and second plurality of texels, and to generate a first color value for the first fragment and a second color value for the second fragment. The color pipeline is also operable to combine the first color value and the first plurality of texels, and to at least begin combining the second color value and the second plurality of texels during the combination of the first color value and the first plurality of texels.

Abstract: A method and apparatus for efficiently rasterizing graphics is provided. The method is intended to be used in combination with a frame buffer that provides fast tile-based addressing. Within this environment, frame buffer memory locations are organized into a tile hierarchy. For this hierarchy, smaller low-level tiles combine to form larger mid-level tiles. Mid-level tiles combine to form high-level tiles. The tile hierarchy may be expanded to include more levels, or collapsed to included fewer levels. A graphics primitive is rasterized by selecting an starting vertex. The low-level tile that includes the starting vertex is then rasterized. The remaining low-level tiles that are included in the same mid-level tile as the starting vertex are then rasterized. Rasterization continues with the mid-level tiles that are included in the same high-level tile as the starting vertex. These mid-level tiles are rasterized by rasterizing their component low-level tiles.

Abstract: A method and apparatus for efficiently rasterizing graphics is provided. The method is intended to be used in combination with a frame buffer that provides fast tile-based addressing. Within this environment, frame buffer memory locations are organized into a tile hierarchy. For this hierarchy, smaller low-level tiles combine to form larger mid-level tiles. Mid-level tiles combine to form high-level tiles. The tile hierarchy may be expanded to include more levels, or collapsed to included fewer levels. A graphics primitive is rasterized by selecting an starting vertex. The low-level tile that includes the starting vertex is then rasterized. The remaining low-level tiles that are included in the same mid-level tile as the starting vertex are then rasterized. Rasterization continues with the mid-level tiles that are included in the same high-level tile as the starting vertex. These mid-level tiles are rasterized by rasterizing their component low-level tiles.

Abstract: A method for generating light values for a set of vertices is disclosed. A set of vertices describing a geometric object is received. Each vertex has a coordinate and is associated with one or more vectors for evaluating a light value. Then, a vertex is selected from the set of vertices for computing a light value at the selected vertex. The light value at the selected vertex is associated with a light source having a coordinate. A selected vector for the selected vertex is then scaled by an inverse magnitude value of a corresponding vector that is associated with a neighboring vertex. The selected vector is scaled to generate an approximately normalized vector. The light value is then evaluated at the selected vertex using the approximately normalized vector such that an accurate normalized vector need not be computed for the selected vertex.

Abstract: A method and apparatus for transferring commands to a graphics processor is provided. The method and apparatus are intended for use in a host computer system having a memory that is addressable by a host processor and a graphics processor. One or more queues of packet descriptors are maintained in the memory of the host computer system. Each packet descriptor includes a pointer to a region of memory known as a packet buffer. Each packet descriptor also includes a ready variable. To pass commands to the graphics processor, a graphics process selects a packet buffer. The packet buffer must have a ready variable that is set to the value false. After selection of the appropriate packet descriptor, the graphics process writes the desired commands into the packet descriptor associated with the selected packet descriptor. The graphics process then sets the ready variable included in the selected packet descriptor to true. The graphics processor traverses the queues of packet descriptors.

Abstract: A method and apparatus for transferring commands to a graphics processor is provided. The method and apparatus are intended for use in a host computer system having a memory that is addressable by a host processor and a graphics processor. One or more queues of packet descriptors are maintained in the memory of the host computer system. Each packet descriptor includes a pointer to a region of memory known as a packet buffer. Each packet descriptor also includes a ready variable. To pass commands to the graphics processor, a graphics process selects a packet buffer. The packet buffer must have a ready variable that is set to the value false. After selection of the appropriate packet descriptor, the graphics process writes the desired commands into the packet descriptor associated with the selected packet descriptor. The graphics process then sets the ready variable included in the selected packet descriptor to true. The graphics processor traverses the queues of packet descriptors.

Abstract: A computer systemprovides dynamic memory allocation for graphics. The computer system includes a memory controller, a unified system memory, and memory clients each having access to the system memory via the memory controller. Memory clients can include a graphics rendering engine, a CPU, an image processor, a data compression/expansion device, an input/output device, a graphics back end device. The computer system provides read/write access to the unified system memory, through the memory controller, for each of the memory clients. Translation hardware is included for mapping virtual addresses of pixel buffers to physical memory locations in the unified system memory. Pixel buffers are dynamically allocated as tiles of physically contiguous memory. Translation hardware is implemented in each of the computational devices, which are included as memory clients in the computer system, including primarily the rendering engine.

Abstract: A method and apparatus for multipass rendering of graphics primitives is provided. The apparatus of the present invention includes a graphics pipeline organized as a sequence of tasks. A set of state information blocks are provided for each pipeline tasks. A host processors stores a set of graphics attributes for each task in the state information blocks. The host processor then sends a first token through the graphics pipeline. The first token causes each task to select the state information block that is associated with that task and the first rendering pass. The host processor then sends a group of graphics primitives through the graphics pipeline. Each tasks performs a graphics transformation on the graphics primitives using the graphics attributes stored in the state information block selected for that task. The host processor then sends a second token through the graphics pipeline.

Abstract: A method and apparatus for efficiently translating virtual to physical addresses is provided. An embodiment of the apparatus includes a TLB descriptor table that includes a series of TLB descriptors. Each TLB descriptor includes an offset that selects a TLB segment within a translation lookaside buffer (TLB). To perform a virtual to physical address translation, a processor sends a virtual address and a descriptor ID to the memory request unit. The descriptor ID is used to select the TLB segment that will be used to perform the virtual to physical address translation. Each TLB segment may have different physical and logical characteristics. In particular, each TLB segment may be associated with a different type of memory page. In this way the present invention, enables the simultaneous use of a range of page types and sizes in a single computer system.

Abstract: A computer system provides dynamic memory allocation for graphics. The computer system includes a memory controller, a unified system memory, and memory clients each having access to the system memory via the memory controller. Memory clients can include a graphics rendering engine, a CPU, an image processor, a data compression/expansion device, an input/output device, a graphics back end device. The computer system provides read/write access to the unified system memory, through the memory controller, for each of the memory clients. Translation hardware is included for mapping virtual addresses of pixel buffers to physical memory locations in the unified system memory. Pixel buffers are dynamically allocated as tiles of physically contiguous memory. Translation hardware is implemented in each of the computational devices, which are included as memory clients in the computer system, including primarily the rendering engine.

Abstract: A memory system that includes a memory controller and memory modules that provide address and control signals to groups of memory components through multiple busses. In one embodiment, each memory module is coupled to an address/control buss. The use of multiple address/control busses provides the necessary bandwidth so as to allow for fast access and control of memory components. Memory components are grouped into banks of memory components with each bank including three memory components. Memory modules are configured with one, two, four, or more banks of memory components on a given memory module. In one embodiment, the memory system includes six 48-bit memory modules that use SDRAM memory components. The six memory modules are used in a set to form a 288-bit memory word. When 16 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 32 megabytes to 2 gigabytes.

Abstract: A method and apparatus for transferring commands to a graphics processor is provided. The method and apparatus are intended for use in a host computer system having a memory that is addressable by a host processor and a graphics processor. One or more queues of packet descriptors are maintained in the memory of the host computer system. Each packet descriptor includes a pointer to a region of memory known as a packet buffer. Each packet descriptor also includes a ready variable. To pass commands to the graphics processor, a graphics process selects a packet buffer. The packet buffer must have a ready variable that is set to the value false. After selection of the appropriate packet descriptor, the graphics process writes the desired commands into the packet descriptor associated with the selected packet descriptor. The graphics process then sets the ready variable included in the selected packet descriptor to true. The graphics processor traverses the queues of packet descriptors.

Abstract: A memory system that includes a memory controller and memory modules that provide address and control signals to groups of memory components through multiple busses. In one embodiment, each memory module is coupled to an address/control buss. The use of multiple address/control busses provides the necessary bandwidth so as to allow for fast access and control of memory components. Memory components are grouped into banks of memory components with each bank including three memory components. Memory modules are configured with one, two, four, or more banks of memory components on a given memory module. In one embodiment, the memory system includes six 48-bit memory modules that use SDRAM memory components. The six memory modules are used in a set to form a 288-bit memory word. When 16 Mbit or 64 Mbit memory components are used, this configuration gives a range of memory configurations from 32 megabytes to 2 gigabytes.