Abstract: A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width.

Abstract: A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width.

Abstract: A context-dependent, multiply binding name resolution system. A name resolver is provided, connected to either a requester's system or a receiver's system, or both. Requests to a given service or domain name are resolved to the appropriate IP address. The intended recipient of the request is resolved based upon a combination of one or more predetermined criteria, including: information about the sender (e.g. geographical location, specific requester identity, etc.); information about the intended recipient (e.g. load balance at the receiver, type of service, etc.); information contained within the request itself (e.g. type of service requested); or other information (time of day, date, random selection of recipient, e.g.). The system is implemented in hardware and/or software, and the resolution criteria can be made interdependent or independent.

Abstract: A data transfer control system for a computer system having a packet-switched data bus, for controlling the transfer of data words from a device having one bus width to a device having a different bus width. The first bus may be the master bus, and the second bus is a bus of a functional unit, such as a memory or other device, connected to the computer system and coupled to the master bus. When the second bus is smaller than the first bus, the data transfer control system accommodates this by transferring only partial words per clock cycle to the second bus, effectively delaying the transference of data to a rate that the second bus can handle. The transfer rate factor is substantially equal to the ratio of the second bus width to the first bus width.

Abstract: In a computer system including a packet-switched bus, a method for requesting transactions such that memory accesses are initiated quickly. A master transmits a first portion of a transaction request packet having multiple portion. A memory controller receives the first portion of the transaction request, which includes a row address portion of a memory address. The memory controller initiates a memory access by applying a row address strobe signal to the row of the memory location in response to receiving the first portion of the request packet, and the master transmits any remaining portion of the transaction request. After the full memory address has been received, it is determined whether data stored at the memory location is to be read from a source other than the memory location. The memory controller aborts the memory access by inhibiting assertion of a column access strobe signal to the memory location if the data is to be read from a source other than the memory location.

Abstract: A low overhead, efficient, and simple protection check circuit is inserted into a data path between a master requester and a target resource such as a memory or input/output device. The master requester initiates a memory request, a pio access request, or a dma transaction directed to the target resource. For example, the master requester may be a processor accessing a memory, a processor performing programmed I/O (pio). Alternatively, the master requester may be a DMA device performing direct memory access of a memory. The protection check circuit is configured at initialization time by an operating system or a privileged software process, then passively monitors all transactions on the data paths, disallowing accesses that fail the protection check operation.

Abstract: Particularly, a system and method are disclosed that enable an author of a subsection of a document quickly to locate referenced information in other parts of the document or different documents prepared by other authors and then incorporate that information in their own document. An author tags information in their document that other authors might wish to import. Each time the document is updated, or as requested by the author, the author's tags and other tags that reference information that is importable by default (e.g., section headings, figures, tables) are exported to a tag repository that is accessible to all other authors. The tag repository also holds the tags generated by other authors from different documents. Using information finding/linking programs any of the authors can search the tag repository and select tags corresponding to information they would like to import into their own documents.

Abstract: In a computer system that utilizes write or read barriers to perform a garbage collection function, instruction execution logic avoids unnecessary calls to the write or read barrier procedure. Each object's header includes a State flag. Each object reference also includes a State flag. Each time an instruction that is the subject of a write or read barrier (e.g., a object reference write instruction) is executed, the State flag of the object reference being processed is inspected by the instruction execution logic. If the State flag in the object reference is set, the write or read barrier procedure is not invoked, because the target object has already been processed by a previous call to the write or read barrier procedure. Otherwise the write or read barrier procedure is invoked. The write or read barrier procedure first checks the State flag in the target object's header. If it is set, the State flag in the target object reference is set and then the procedure exits.

Abstract: This invention describes a link-by-link flow control method for packet-switched uniprocessor and multiprocessor computer systems that maximizes system resource utilization and throughput, and minimizes system latency. The computer system comprises one or more master interfaces, one or more slave interfaces, and an interconnect system controller which provides dedicated transaction request queues for each master interface and controls the forwarding of transactions to each slave interface. The master interface keeps track of the number of requests in the dedicated queue in the system controller, and the system controller keeps track of the number of requests in each slave interface queue. Both the master interface, and system controller know the maximum capacity of the queue immediately downstream from it, and does not issue more transaction requests than what the downstream queue can accommodate.

Abstract: A multiprocessor computer system has a multiplicity of sub-systems and a main memory coupled to a system controller. Some of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective set of master cache tags (Etags), including one Etag for each data block stored by the cache memory. Each data processor includes an interface for sending memory transaction requests to the system controller and for receiving cache transaction requests from the system controller corresponding to memory transaction requests by other ones of the data processors. The system controller includes transaction activation logic for activating each said memory transaction request when it meets predefined activation criteria, and for blocking each said memory transaction request until the predefined activation criteria are met.

Abstract: An apparatus and method for handling interrupt requests from any of a plurality of interrupters to any of a plurality of interrupt handlers. Each interrupt handler includes an interrupt input request queue for holding a plurality of incoming interrupt requests. A system controller is connected to the interrupters and the interrupt handlers, and includes an input queue coupled to each interrupter for receiving a plurality of interrupt requests. The system controller includes a processor and a memory storing instructions for controlling its operation. The system controller also includes an output queue coupled to each interrupt handler (which in many cases will also be interrupters), and a counter for monitoring the current number, at any given time, of interrupt requests pending in each of the interrupt input queues in the interrupt handlers.

Abstract: A computer system has a CPU, a stack cache and a main memory. The main memory is a conventional untagged memory, where each memory location is a word having a bit size that is an integer power of 2 (e.g., 32, 64 or 128 bits per word). However, at least one stack cache associated with the CPU (and preferably integrated with the CPU on the same semiconductor circuit or in the same chip set) is a tagged memory where each data word of the stack cache has an associated tag. Whenever the stack cache overflows with data, at least a portion of the contents of the stack cache are stored in a previously established location in main memory so as to make room for storing additional data in the stack cache. In this stack cache swap out operation, the data values and tags in N evaluation stack entries of the evaluation stack cache are copied to the previously established main memory location.

Abstract: A data processor supports the use of multiple memory models by computer programs. At a device external to a data processor, such as a memory controller, memory transactions requests are received from the data processor. Each memory transaction request has associated therewith a memory model selected from a predefined plurality of memory models. In a preferred embodiment, the predefined memory models supported are SSO (strong sequential order), TSO (total store order), PSO (partial store order) and RMO (relaxed memory order). Data representing pending memory transactions are stored in one or more pending transaction buffers and a pending transaction status array. The pending transaction status data includes memory transaction order data that indicates which of the pending memory transactions can be performed before other ones of the pending memory transactions.

Abstract: In a cluster of computer nodes, each node has network interface and at least one processor. Transmission of a multipart message from a first node to a second node is initiated by sending to a network interface of the first node a sequence of PIO store and DMA store commands, each PIO store and DMA store command specifying a respective component of the multipart message to be stored in a respective specified memory mapped location in the second node, the sequence of the PIO store and DMA store commands corresponding to a predefined message component order. The first node's network interface packetizes the sequence of PIO and DMA commands to generate an ordered stream of data transfer packets whose order corresponds to the predefined message component order, and transmits the ordered stream of data transfer packets to the second node so as to store the respective components of the multipart message in their respective specified memory locations in the second node in the predefined message component order.

Abstract: A power sequence controller contains wakeup logic for responding to each wakeup event signal intercepted by the power sequence controller. The wakeup logic compares the intercepted wakeup event signal with a wakeup filter mask to determine if the wakeup event signal should be processed or ignored. If the wakeup event signal requires processing, the wakeup logic transitions the system's processor to a working state. The wakeup logic also determines if the intercepted wakeup event signal requires software processing. If so, a non-zero value associated with the wakeup event signal is stored in an interrupt source register, which causes the processor to execute an interrupt handler procedure and process the wakeup event signal when it transitions to a working state. The wakeup logic also evaluates the processor sleep state to determine if transitioning the processor from the sleep state to a working state requires execution of a processor wakeup procedure to return the processor to normal operation.

Abstract: The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e.

Abstract: In an object oriented computer system, a root set of object references includes object references stored in the computer system's registers, as well as object references stored in activation records in the program stack. Whenever a method is invoked, a corresponding activation record is stored on the program stack. The activation record includes the invocation address for the method called as well as parameters passed to the called method. A class loader, which loads object classes into memory, determines the locations of the object references in the activation records associated with each method in a loaded object class. A list of offset values for each method activation record is stored by the class loader in a hash table data structure at a location in the hash table data structure determined by hashing the unique invocation address assigned to the method.

Abstract: A computer system is disclosed including a memory subsystem and a processor subsystem having an external cache and an external mechanism for invalidating cached datablocks in the processor subsystem and for reducing false invalidation operations. The processor subsystem issues a write invalidate message to the memory subsystem that specifies a datablock and that includes an invalidate advisory indication that indicates whether the datablock is present in the external cache. The invalidate advisory indication determines whether the memory subsystem returns an invalidate message to the processor subsystem for the write invalidate operation.

Abstract: The present invention provides a scalable, modular and pipelined distributed bus arbitration system for efficiently resolving bus contention between sub-systems, e.g., processors, coupled to a common system bus. The arbitration system includes a plurality of distributed bus arbiters which receives the bus requests from the sub-systems and independently determine the next bus master. The arbitration protocol enables the arbitration process to be eliminated from the critical timing path thereby allowing the system to operate at the maximum system clock frequency possible for a given integrated circuit (IC) technology to reduce overall system clock latencies. Any change among the sub-systems during an arbitration clock cycle is based on any system bus request(s) which are active during a clock cycle immediately preceding the arbitration clock cycle, and is independent of any system bus request(s) asserted during the arbitration clock cycle. In addition, the arbitration protocol treats a current bus master, i.e.

Abstract: A multi-processor computer system is disclosed that reduces the occurrences of invalidate and copyback operations through a memory interconnect by disabling a first write optimization of a cache coherency protocol for data that is not likely to be written by a requesting processor. Such data include read-only code segments. The code segments, including instructions and data, are shared among the multiple processors. The requesting processor generates a Read to Share Always request upon a cache miss of a read-only datablock, and generates a Read to Share request otherwise. The Read to Share Always request results in the datablock stored in cache memory being labeled as in a "shared" state, while the Read to Share request results in the datablock being labeled as in an "exclusive" state.