Patents by Inventor ZAICHEN CHEN

ZAICHEN CHEN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11658176
    Abstract: An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: May 23, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Zaichen Chen, Akram A. Salman, Binghua Hu
  • Publication number: 20220223580
    Abstract: An electrostatic discharge protection system with a node adapted to receive a signal and threshold detecting circuitry coupled to the node. The system includes an IGBT having an IGBT gate coupled to an output of the threshold detecting circuitry, a resistor coupled between an IGBT emitter of the IGBT and a low reference potential node, and a BJT having a BJT base coupled to the IGBT emitter.
    Type: Application
    Filed: May 16, 2021
    Publication date: July 14, 2022
    Inventors: James Paul DiSarro, Aravind Chennimalai Appaswamy, Zaichen Chen
  • Publication number: 20220199611
    Abstract: In an example, an electronic device includes a first well having a first conductivity type within a semiconductor substrate and a second well having a second opposite conductivity type within the semiconductor substrate and touching the first well. The device further includes a third well having the first conductivity type within the second well. A metallic structure in direct contact with at least a portion of a surface of the third well thereby forms a Schottky barrier between the third well and the metallic structure.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventors: Zaichen CHEN, Akram Ali SALMAN, Henry Litzmann EDWARDS
  • Publication number: 20210408270
    Abstract: An integrated circuit includes a semiconductor substrate having a doped region, e.g. a DWELL, with a first conductivity type. A source region is located within the doped region, the source region having a second opposite conductivity type. A drain region having the second conductivity type is spaced apart from the source region. A gate electrode is located between the source region and the drain region, the gate electrode partially overlapping the doped region. A body region having the first conductivity type is located within the doped region. A dielectric layer forms a closed path around the body region.
    Type: Application
    Filed: June 24, 2021
    Publication date: December 30, 2021
    Inventors: Zaichen Chen, Akram Ali Salman
  • Publication number: 20210013193
    Abstract: An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.
    Type: Application
    Filed: September 28, 2020
    Publication date: January 14, 2021
    Inventors: ZAICHEN CHEN, AKRAM A. SALMAN, BINGHUA HU
  • Patent number: 10790275
    Abstract: An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: September 29, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Zaichen Chen, Akram A. Salman, Binghua Hu
  • Publication number: 20200203333
    Abstract: An integrated circuit (IC) includes a semiconductor substrate having a first conductivity type and a transistor formed within the substrate that includes a buried layer having a second conductivity type. A first doped region, located between the buried layer and a surface of the substrate, has the first conductivity type and a second doped region, extending from the substrate surface to the buried layer, has the second conductivity type. A third doped region, located between the buried layer and the surface and between the first doped region and the second doped region, has the second conductivity type and a first dopant concentration. A fourth doped region, located between the third doped region and the substrate surface and between the first doped region and the second doped region, has a second dopant concentration less than the first dopant concentration. A method of fabricating the IC is also shown.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 25, 2020
    Inventors: Zaichen Chen, Akram Ali Salman
  • Publication number: 20200161292
    Abstract: An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.
    Type: Application
    Filed: November 21, 2018
    Publication date: May 21, 2020
    Inventors: ZAICHEN CHEN, AKRAM A. SALMAN, BINGHUA HU