Abstract: The present disclosure generally relates to an insulated gate bipolar junction transistor (IGBJT). In an example, a semiconductor device includes a semiconductor substrate, a first well in the semiconductor substrate, a second well in the semiconductor substrate, a gate electrode over the semiconductor substrate, a source region in the second well, a collector region in the second well, an emitter region in the first well, a drain region in the first well, and a silicide on the source region and the collector region. The first well, source region, and drain region are doped with a first conductivity type. The second well, collector region, and emitter region are doped with a second conductivity type opposite from the first conductivity type. The gate electrode extends laterally over the first well and the second well. The gate electrode is laterally between the source region and the emitter region.

Abstract: An electrostatic discharge protection system with a node adapted to receive a signal and threshold detecting circuitry coupled to the node. The system includes an IGBT having an IGBT gate coupled to an output of the threshold detecting circuitry, a resistor coupled between an IGBT emitter of the IGBT and a low reference potential node, and a BJT having a BJT base coupled to the IGBT emitter.

Abstract: An integrated circuit includes a semiconductor substrate having a doped region, e.g. a DWELL, with a first conductivity type. A source region is located within the doped region, the source region having a second opposite conductivity type. A drain region having the second conductivity type is spaced apart from the source region. A gate electrode is located between the source region and the drain region, the gate electrode partially overlapping the doped region. A body region having the first conductivity type is located within the doped region. A dielectric layer forms a closed path around the body region.

Abstract: An electrostatic discharge protection system with a node adapted to receive a signal and threshold detecting circuitry coupled to the node. The system includes an IGBT having an IGBT gate coupled to an output of the threshold detecting circuitry, a resistor coupled between an IGBT emitter of the IGBT and a low reference potential node, and a BJT having a BJT base coupled to the IGBT emitter.

Abstract: An electrostatic discharge protection system with a node adapted to receive a signal and threshold detecting circuitry coupled to the node. The system includes an IGBT having an IGBT gate coupled to an output of the threshold detecting circuitry, a resistor coupled between an IGBT emitter of the IGBT and a low reference potential node, and a BJT having a BJT base coupled to the IGBT emitter.

Abstract: An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.

Abstract: An electrostatic discharge protection system with a node adapted to receive a signal and threshold detecting circuitry coupled to the node. The system includes an IGBT having an IGBT gate coupled to an output of the threshold detecting circuitry, a resistor coupled between an IGBT emitter of the IGBT and a low reference potential node, and a BJT having a BJT base coupled to the IGBT emitter.

Abstract: In an example, an electronic device includes a first well having a first conductivity type within a semiconductor substrate and a second well having a second opposite conductivity type within the semiconductor substrate and touching the first well. The device further includes a third well having the first conductivity type within the second well. A metallic structure in direct contact with at least a portion of a surface of the third well thereby forms a Schottky barrier between the third well and the metallic structure.

Abstract: An integrated circuit includes a semiconductor substrate having a doped region, e.g. a DWELL, with a first conductivity type. A source region is located within the doped region, the source region having a second opposite conductivity type. A drain region having the second conductivity type is spaced apart from the source region. A gate electrode is located between the source region and the drain region, the gate electrode partially overlapping the doped region. A body region having the first conductivity type is located within the doped region. A dielectric layer forms a closed path around the body region.

Abstract: An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.

Abstract: An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.

Abstract: An integrated circuit (IC) includes a semiconductor substrate having a first conductivity type and a transistor formed within the substrate that includes a buried layer having a second conductivity type. A first doped region, located between the buried layer and a surface of the substrate, has the first conductivity type and a second doped region, extending from the substrate surface to the buried layer, has the second conductivity type. A third doped region, located between the buried layer and the surface and between the first doped region and the second doped region, has the second conductivity type and a first dopant concentration. A fourth doped region, located between the third doped region and the substrate surface and between the first doped region and the second doped region, has a second dopant concentration less than the first dopant concentration. A method of fabricating the IC is also shown.

Abstract: An electronic device includes a substrate having a second conductivity type including a semiconductor surface layer with a buried layer (BL) having a first conductivity type. In the semiconductor surface layer is a first doped region (e.g., collector) and a second doped region (e.g., emitter) both having the first conductivity type, with a third doped region (e.g., a base) having the second conductivity type within the second doped region, wherein the first doped region extends below and lateral to the third doped region. At least one row of deep trench (DT) isolation islands are within the first doped region each including a dielectric liner extending along a trench sidewall from the semiconductor surface layer to the BL with an associated deep doped region extending from the semiconductor surface layer to the BL. The deep doped regions can merge forming a merged deep doped region that spans the DT islands.