Abstract: Devices and techniques for amplifying a signal are disclosed. For instance, an amplifier includes an input node and an output node; a first gain segment including: a first transistor, where a gate of the first transistor is coupled to the input node, a first terminal of the first transistor is coupled to a ground, and a second terminal of the first transistor is coupled to the output node; a second gain segment including: a second transistor, where a gate of the second transistor is coupled to the input node, a first terminal of the second transistor is coupled to the ground, and a second terminal of the second transistor is coupled to the output node, where the first gain segment and the second gain segment are arranged in parallel with respect to the output node; and a bias circuit.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for wireless communication implemented with harmonic cancellation. One example implementation includes a polar transmitter having at least one amplifier having an input configured to receive a phase-modulated signal to be amplified based on an amplitude-modulated signal, a harmonic cancellation circuit coupled to the input of the at least one amplifier, the harmonic cancellation circuit being configured to cancel at least one of an even harmonic or an odd harmonic of a transmission signal at an output of the polar transmitter, a controller having an output coupled to one or more control inputs of the harmonic cancellation circuit, and a feedback path between an output of the at least one amplifier and an input of the controller.

Abstract: Certain aspects of the present disclosure provide apparatus and techniques for wireless communication implemented with harmonic cancellation. One example implementation includes a polar transmitter having at least one amplifier having an input configured to receive a phase-modulated signal to be amplified based on an amplitude-modulated signal, a harmonic cancellation circuit coupled to the input of the at least one amplifier, the harmonic cancellation circuit being configured to cancel at least one of an even harmonic or an odd harmonic of a transmission signal at an output of the polar transmitter, a controller having an output coupled to one or more control inputs of the harmonic cancellation circuit, and a feedback path between an output of the at least one amplifier and an input of the controller.

Abstract: The present disclosure relates to a circuit for suppressing unwanted magnetic interference. The circuit can have a transformer having a first coil, a first pair of input terminals, and a first pair of output terminals. The transformer can produce a first magnetic field. The circuit can also have a harmonic trap. The harmonic trap can have a second coil and a second pair of input terminals operably coupled to the first pair of input terminals. The harmonic trap can produce a second magnetic field opposing the first magnetic field. The harmonic trap can suppress electrical signals of at least one of the first input terminals and the first output terminals of the transformer at a resonant frequency of the harmonic trap. The harmonic trap can also suppress the first magnetic field in a far field.

Abstract: The present disclosure relates to a circuit for suppressing unwanted magnetic interference. The circuit can have a transformer having a first coil, a first pair of input terminals, and a first pair of output terminals. The transformer can produce a first magnetic field. The circuit can also have a harmonic trap. The harmonic trap can have a second coil and a second pair of input terminals operably coupled to the first pair of input terminals. The harmonic trap can produce a second magnetic field opposing the first magnetic field. The harmonic trap can suppress electrical signals of at least one of the first input terminals and the first output terminals of the transformer at a resonant frequency of the harmonic trap. The harmonic trap can also suppress the first magnetic field in a far field.

Abstract: The present disclosure relates to composite inductor structures for use in integrated circuits. There is provided a composite inductor structure comprising a first inductor coil and a second inductor coil. The second inductor coil comprises a multi-turn loop that surrounds the first inductor coil. The first inductor coil comprises two multi-turn loops which are connected in a figure-of-eight configuration about a central terminal so as to cause a current flowing in a first loop of the multi-turn loops to circulate around the first loop in a first rotational direction, and a current flowing in a second loop of the multi-turn loops to circulate around the second loop in a second rotational direction opposite the rotational direction of current flow in the first loop, said direction of current flow in the first and second loops being mirror images of each other.

Abstract: The present disclosure relates to composite inductor structures for use in integrated circuits. There is provided a composite inductor structure comprising a first inductor coil and a second inductor coil. The second inductor coil comprises a multi-turn loop that surrounds the first inductor coil. The first inductor coil comprises two multi-turn loops which are connected in a figure-of-eight configuration about a central terminal so as to cause a current flowing in a first loop of the multi-turn loops to circulate around the first loop in a first rotational direction, and a current flowing in a second loop of the multi-turn loops to circulate around the second loop in a second rotational direction opposite the rotational direction of current flow in the first loop, said direction of current flow in the first and second loops being mirror images of each other.

Abstract: A radially segmented antenna design is described. In an embodiment, the radially segmented antenna is formed from multiple patches which are arranged in a ring around the central point of the radially segmented antenna. Each patch is shaped to form a segment of the ring and is separated from the two adjacent patches. In operation, alternate patches in the ring may be used for transmitting and the remaining patches may be terminated in an open circuit or may be used for receiving. Alternatively, all the patches in the ring may be used for transmitting or receiving. In some examples, there may be more than one concentric ring of patches within the radially segmented antenna and the additional rings may be located on the same face of the antenna as the first ring of patches, or on the opposite face of the antenna.

Abstract: Under bump passive structures, such as capacitors and inductors, may be formed using the post-processing layers in wafer level packaging. In an embodiment, a packaged semiconductor device is described which includes an under-bump capacitor formed in semiconductor device post-processing layers. As part of the post-processing a first dielectric layer is deposited on the active face of a semiconductor die and then in sequence a first metal layer, second dielectric layer and second metal layer are deposited. The under-bump capacitor is formed from a lower plate in the first metal layer and an upper plate in the second metal layer, the plates being separated by the second dielectric layer. In order to increase capacitance, the capacitor may be formed over one or more openings in the first dielectric layer, such that the layers forming the capacitor are no longer planar but follow the underlying topology.

Abstract: A radially segmented antenna design is described. In an embodiment, the radially segmented antenna is formed from multiple patches which are arranged in a ring around the central point of the radially segmented antenna. Each patch is shaped to form a segment of the ring and is separated from the two adjacent patches. In operation, alternate patches in the ring may be used for transmitting and the remaining patches may be terminated in an open circuit or may be used for receiving. Alternatively, all the patches in the ring may be used for transmitting or receiving. In some examples, there may be more than one concentric ring of patches within the radially segmented antenna and the additional rings may be located on the same face of the antenna as the first ring of patches, or on the opposite face of the antenna.

Abstract: Under bump passive structures in wafer level packaging and methods of fabricating these structures are described. In an embodiment, a packaged semiconductor device is described which includes an under-bump capacitor formed in semiconductor device post-processing layers. As part of the post-processing a first dielectric layer is deposited on the active face of a semiconductor die and then in sequence a first metal layer, second dielectric layer and second metal layer are deposited. The under-bump capacitor is formed from a lower plate in the first metal layer and an upper plate in the second metal layer, the plates being separated by the second dielectric layer. In order to increase capacitance, the capacitor may be formed over one or more openings in the first dielectric layer, such that the layers forming the capacitor are no longer planar but follow the underlying topology.

Abstract: An electronic component comprising an integrated device and a plurality of packaging layers in which routing between locations on the device and lands on the surface of the component is provided by a redistribution layer. The redistribution layer may be routed below the extent of a contact pad on the surface by providing a channel through the via and redistribution layers underneath that land.

Abstract: A low cost flexible substrate is described which comprises a thin metal foil and a layer of solder mask. The metal foil layer is patterned to create tracks and lands for solder bonding and/or wirebonding and the layer of solder mask is patterned to create openings for solder bonding, wirebonding and/or for mounting the die. The substrate may be used as a package substrate to create a packaged die or may be used as a replacement for more expensive flexible printed circuit boards.

Abstract: An electronic component comprising an integrated device and a plurality of packaging layers in which routing between locations on the device and lands on the surface of the component is provided by a redistribution layer. The redistribution layer may be routed below the extent of a contact pad on the surface by providing a channel through the via and redistribution layers underneath that land.

Abstract: A low cost flexible substrate is described which comprises a thin metal foil and a layer of solder mask. The metal foil layer is patterned to create tracks and lands for solder bonding and/or wirebonding and the layer of solder mask is patterned to create openings for solder bonding, wirebonding and/or for mounting the die. The substrate may be used as a package substrate to create a packaged die or may be used as a replacement for more expensive flexible printed circuit boards.