Patents by Inventor Zainab Ismail

Zainab Ismail has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7968148
    Abstract: An integrated circuit system includes providing an integrated circuit wafer; applying a first cleaning solution over the integrated circuit wafer; and applying a second cleaning solution over the integrated circuit wafer to prevent or remove a defect resulting from the first cleaning process.
    Type: Grant
    Filed: September 13, 2007
    Date of Patent: June 28, 2011
    Assignee: Globalfoundries Singapore Pte. Ltd.
    Inventors: Yin-Min Felicia Goh, Zainab Ismail, Yong Siang Tan, Ling Zhi Tan, Sin Ping Chiew
  • Publication number: 20080069958
    Abstract: An integrated circuit system includes providing an integrated circuit wafer; applying a first cleaning solution over the integrated circuit wafer; and applying a second cleaning solution over the integrated circuit wafer to prevent or remove a defect resulting from the first cleaning process.
    Type: Application
    Filed: September 13, 2007
    Publication date: March 20, 2008
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Yin-Min Felicia Goh, Zainab Ismail, Yong Siang Tan, Ling Zhi Tan, Sin Ping Chiew
  • Patent number: 7268048
    Abstract: Methods of preparing conductive regions such as source/drain regions for silicidation procedures, has been developed. The methods feature removal of native oxide as well as removal of deposited arsenic based defects from conductive surfaces prior to deposition of a metal component of subsequently formed metal silicide regions. Arsenic ions implanted for N type source/drain regions are also implanted into insulator regions such as insulator filled shallow trench isolation regions. A hydrofluoric acid cycle used as a component of the pre-silicidation preparation procedure can release arsenic from the shallow trench isolation regions in the form of arsenic based defects, which in turn can re-deposit on the surface of source/drain region. Therefore pre-silicidation preparation treatments described in this invention feature removal of both native oxide and arsenic based defects from conductive surfaces prior to metal silicide formation.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: September 11, 2007
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yin-Min Felicia Goh, Simon Chooi, Teck Wee Lim, Vincent Sih, Chian Yuh Sin, Ping Yu Ee, Zainab Ismail, Cher Sian Chua
  • Publication number: 20060030095
    Abstract: Methods of preparing conductive regions such as source/drain regions for silicidation procedures, has been developed. The methods feature removal of native oxide as well as removal of deposited arsenic based defects from conductive surfaces prior to deposition of a metal component of subsequently formed metal silicide regions. Arsenic ions implanted for N type source/drain regions are also implanted into insulator regions such as insulator filled shallow trench isolation regions. A hydrofluoric acid cycle used as a component of the pre-silicidation preparation procedure can release arsenic from the shallow trench isolation regions in the form of arsenic based defects, which in turn can re-deposit on the surface of source/drain region. Therefore pre-silicidation preparation treatments described in this invention feature removal of both native oxide and arsenic based defects from conductive surfaces prior to metal silicide formation.
    Type: Application
    Filed: August 6, 2004
    Publication date: February 9, 2006
    Inventors: Yin-Min Goh, Simon Chooi, Teck Lim, Vincent Sih, Chian Sin, Ping Ee, Zainab Ismail, Cher Chua