Patents by Inventor Zainab Nasreen Zaidi
Zainab Nasreen Zaidi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11475973Abstract: A system and method for virtually addressing an array of accelerator tiles of a mixed-signal integrated circuit includes testing each of a plurality of distinct matrix multiply accelerator (MMA) tiles of a grid of MMA tiles, the grid of MMA tiles being defined by the plurality of distinct grid of MMA tiles being arranged in a plurality of rows and a plurality of columns along an integrated circuit, each of the plurality of distinct MMA tiles within the grid of MMA tiles having a distinct physical address on the integrated circuit; identifying one or more defective MMA tiles within the grid of MMA tiles based on the testing; and configuring the grid of MMA tiles with a plurality of virtual addresses for routing data to or routing data from one or more non-defective MMA tiles of grid of MMA tiles based on identifying the one or more defective MMA tiles.Type: GrantFiled: May 26, 2021Date of Patent: October 18, 2022Assignee: Mythic, Inc.Inventors: Malav Parikh, Zainab Nasreen Zaidi, Sergio Schuler, Natarajan Seshan, Raul A. Garibay, Jr., David Fick
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Publication number: 20220276983Abstract: A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.Type: ApplicationFiled: May 16, 2022Publication date: September 1, 2022Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
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Patent number: 11360932Abstract: A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.Type: GrantFiled: February 13, 2020Date of Patent: June 14, 2022Assignee: Mythic, Inc.Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
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Publication number: 20210280266Abstract: A system and method for virtually addressing an array of accelerator tiles of a mixed-signal integrated circuit includes testing each of a plurality of distinct matrix multiply accelerator (MMA) tiles of a grid of MMA tiles, the grid of MMA tiles being defined by the plurality of distinct grid of MMA tiles being arranged in a plurality of rows and a plurality of columns along an integrated circuit, each of the plurality of distinct MMA tiles within the grid of MMA tiles having a distinct physical address on the integrated circuit; identifying one or more defective MMA tiles within the grid of MMA tiles based on the testing; and configuring the grid of MMA tiles with a plurality of virtual addresses for routing data to or routing data from one or more non-defective MMA tiles of grid of MMA tiles based on identifying the one or more defective MMA tiles.Type: ApplicationFiled: May 26, 2021Publication date: September 9, 2021Inventors: Malav Parikh, Zainab Nasreen Zaidi, Sergio Schuler, Natarajan Seshan, Raul A. Garibay, Jr., David Fick
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Patent number: 11049586Abstract: A system and method for virtually addressing an array of accelerator tiles of a mixed-signal integrated circuit includes testing each of a plurality of distinct matrix multiply accelerator (MMA) tiles of a grid of MMA tiles, the grid of MMA tiles being defined by the plurality of distinct grid of MMA tiles being arranged in a plurality of rows and a plurality of columns along an integrated circuit, each of the plurality of distinct MMA tiles within the grid of MMA tiles having a distinct physical address on the integrated circuit; identifying one or more defective MMA tiles within the grid of MMA tiles based on the testing; and configuring the grid of MMA tiles with a plurality of virtual addresses for routing data to or routing data from one or more non-defective MMA tiles of grid of MMA tiles based on identifying the one or more defective MMA tiles.Type: GrantFiled: November 3, 2020Date of Patent: June 29, 2021Assignee: Mythic, Inc.Inventors: Malav Parikh, Zainab Nasreen Zaidi, Sergio Schuler, Natarajan Seshan, Raul A. Garibay, Jr., David Fick
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Publication number: 20210158889Abstract: A system and method for virtually addressing an array of accelerator tiles of a mixed-signal integrated circuit includes testing each of a plurality of distinct matrix multiply accelerator (MMA) tiles of a grid of MMA tiles, the grid of MMA tiles being defined by the plurality of distinct grid of MMA tiles being arranged in a plurality of rows and a plurality of columns along an integrated circuit, each of the plurality of distinct MMA tiles within the grid of MMA tiles having a distinct physical address on the integrated circuit; identifying one or more defective MMA tiles within the grid of MMA tiles based on the testing; and configuring the grid of MMA tiles with a plurality of virtual addresses for routing data to or routing data from one or more non-defective MMA tiles of grid of MMA tiles based on identifying the one or more defective MMA tiles.Type: ApplicationFiled: November 3, 2020Publication date: May 27, 2021Inventors: Malav Parikh, Zainab Nasreen Zaidi, Sergio Schuler, Natarajan Seshan, Raul A. Garibay, JR., David Fick
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Publication number: 20200192858Abstract: A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.Type: ApplicationFiled: February 13, 2020Publication date: June 18, 2020Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
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Patent number: 10606797Abstract: A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.Type: GrantFiled: July 1, 2019Date of Patent: March 31, 2020Assignee: Mythic, Inc.Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
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Publication number: 20200012617Abstract: Systems and methods include an integrated circuit that includes a plurality of computing tiles, wherein each of the plurality of computing tiles includes: a matrix multiply accelerator, a computing processing circuit; and a flow scoreboard module; a local data buffer, wherein the plurality of computing tiles together define an intelligence processing array; a network-on-chip system comprising: a plurality of network-on-chip routers establishing a communication network among the plurality of computing tiles, wherein each network-on-chip router is in operable communication connection with at least one of the plurality of computing tiles and a distinct network-on-chip router of the plurality of network-on-chip routers; and an off-tile buffer that is arranged in remote communication with the plurality of computing tiles, wherein the off-tile buffer stores raw input data and/or data received from an upstream process or an upstream device.Type: ApplicationFiled: July 1, 2019Publication date: January 9, 2020Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
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Publication number: 20200012616Abstract: A system and method for automated data propagation and automated data processing within an integrated circuit includes an intelligence processing integrated circuit comprising at least one intelligence processing pipeline, wherein the at least one intelligence processing pipeline includes: a main data buffer that stores input data; a plurality of distinct intelligence processing tiles, wherein each distinct intelligence processing tile includes a computing circuit and a local data buffer; a token-based governance module, the token-based governance module implementing: a first token-based control data structure; a second token-based control data structure, wherein the first token-based control data structure and the second-token based control data operate in cooperation to control an automated flow of the input data and/or an automated processing of the input data through the at least one intelligence processing pipeline.Type: ApplicationFiled: July 1, 2019Publication date: January 9, 2020Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
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Patent number: 10521395Abstract: Systems and methods include an integrated circuit that includes a plurality of computing tiles, wherein each of the plurality of computing tiles includes: a matrix multiply accelerator, a computing processing circuit; and a flow scoreboard module; a local data buffer, wherein the plurality of computing tiles together define an intelligence processing array; a network-on-chip system comprising: a plurality of network-on-chip routers establishing a communication network among the plurality of computing tiles, wherein each network-on-chip router is in operable communication connection with at least one of the plurality of computing tiles and a distinct network-on-chip router of the plurality of network-on-chip routers; and an off-tile buffer that is arranged in remote communication with the plurality of computing tiles, wherein the off-tile buffer stores raw input data and/or data received from an upstream process or an upstream device.Type: GrantFiled: July 1, 2019Date of Patent: December 31, 2019Assignee: Mythic, Inc.Inventors: David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy, Erik Schlanger, Sergio Schuler, Zainab Nasreen Zaidi, Alex Dang-Tran, Raul Garibay, Bryant Sorensen
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Publication number: 20190094939Abstract: A method and apparatus is disclosed for minimizing power virus in a network on chip. The method includes an operational metric related to a node with at least one threshold, the node configured to manage communication of a first number of outbound transactions; determining, based on the comparison, a second number of outbound transactions from the first number of outbound transactions that are allowed from the node; and communicating the second number of outbound transactions. An apparatus for minimizing power virus in a network on chip is also disclosed.Type: ApplicationFiled: September 22, 2017Publication date: March 28, 2019Inventors: Hans Yeager, Thomas Basnight, Zainab Nasreen Zaidi, Cesar Aaron Ramirez
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Publication number: 20190089619Abstract: Aspects of the present disclosure propose techniques for testing a network on chip (NoC). An exemplary method may generally include generating, at a source node of the NoC, a first plurality of packets according to a first pre-defined pattern of a plurality of pre-defined patterns, wherein each pre-defined pattern is designed to provoke transients in the NoC, generating, at the source node of the NoC, a second plurality of packets according to the first pre-defined pattern of the plurality of pre-defined patterns, generating the transients in the NoC by transmitting the first plurality of packets and thereafter transmitting the second plurality of packets, and verifying at least one of the first plurality of packets or the second plurality of packets are successfully received at a destination node of the NoC despite the generated transients.Type: ApplicationFiled: September 21, 2017Publication date: March 21, 2019Applicant: QUALCOMM IncorporatedInventors: Hans YEAGER, Scott LEMKE, Thomas BASNIGHT, Zainab Nasreen ZAIDI
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Publication number: 20190020586Abstract: Selective insertion of a deadlock recovery buffer in a bus interconnect for deadlock recovery is provided. A bus interconnect is provided that includes router nodes configured to receive new bus transaction messages from agent devices. The router nodes route the received bus transaction messages to other destination router nodes in the bus interconnect to be communicated to designated agent devices. To recover from a deadlock condition when buffers of all router nodes are full, thus halting forward progress of bus transaction messages, a deadlock recovery circuit is provided. The deadlock recovery circuit is configured to detect a bus deadlock condition in the bus interconnect. In response, the deadlock recovery circuit is configured to insert a deadlock recovery buffer that has additional buffer entries in the bus interconnect as another router node to allow forward progress of bus transaction messages to continue to recover from the deadlock condition.Type: ApplicationFiled: July 14, 2017Publication date: January 17, 2019Inventors: Ravi Karanam, Thomas Basnight, Zainab Nasreen Zaidi