Abstract: Disclosed are a hardware acceleration system for data processing, and a chip. The hardware acceleration system is configured to read and write its external Double Date Rate (DDR) storage unit. The hardware acceleration system includes a control unit, a data reading unit, a Static Random Access Memory (SRAM) dedicated storage unit, a register configuration unit, an arithmetic unit and a data write-back unit. Under the monitoring and control of the control unit, for each to-be-processed data block, the data reading unit only uses one read operation to complete the reading of a current to-be-processed data block from the DDR storage unit, and the data write-back unit only uses one write operation to complete the writing-back of all operation results of the current to-be-processed data block to the DDR storage unit.

Abstract: Disclosed are a Pulse Width Modulation (PWM) generation circuit, a processing circuit and a chip. The PWM generation circuit is used for controlling a rotation speed of an external motor system. The PWM generation circuit includes a second clock prescaler and a PWM signal generator. A frequency division output end of the second clock prescaler is connected to a data input end of the PWM signal generator. The PWM signal generator includes an output frequency divider and a comparator. A clock output end of the output frequency divider is connected to a comparison input end of the comparator. By means of the technical solution, PWM signals with different duty ratios.

Abstract: Disclosed are an acceleration control system based on a binarization algorithm, a chip, and a robot, which is configured to read and write an external image memory by means of an AHB bus. The acceleration control system includes a main control module, a binarization module, and a binarization FIFO module, and the main control module is configured to control the AHB bus to read pixel data to be processed in the image memory and control current pixel data in the AHB bus to be burst-transmitted to the binarization module for processing when a main state machine is in a burst read mode state, and meanwhile control the binarization FIFO module to read binarized data obtained and when all of the pixel data stored in the image memory is processed, and it is notified to send an interrupt instruction to a CPU.

Abstract: Disclosed are a Pulse Width Modulation (PWM) generation circuit, a processing circuit and a chip. The PWM generation circuit is used for controlling a rotation speed of an external motor system. The PWM generation circuit includes a second clock prescaler and a PWM signal generator. A frequency division output end of the second clock prescaler is connected to a data input end of the PWM signal generator. The PWM signal generator includes an output frequency divider and a comparator. A clock output end of the output frequency divider is connected to a comparison input end of the comparator. By means of the technical solution, PWM signals with different duty ratios.

Abstract: Disclosed are an acceleration control system based on a binarization algorithm, a chip, and a robot, which is configured to read and write an external image memory by means of an AHB bus. The acceleration control system includes a main control module, a binarization module, and a binarization FIFO module, and the main control module is configured to control the AHB bus to read pixel data to be processed in the image memory and control current pixel data in the AHB bus to be burst-transmitted to the binarization module for processing when a main state machine is in a burst read mode state, and meanwhile control the binarization FIFO module to read binarized data obtained and when all of the pixel data stored in the image memory is processed, and it is notified to send an interrupt instruction to a CPU.

Abstract: A method for adjusting a reference voltage is provided, including: decoding a default code configured in a reference voltage register in a chip to obtain an actual reference voltage; comparing the actual reference voltage with a benchmark value to obtain a deviation value between the two; configuring an adjustment code according to the deviation value; and, burning the adjustment code into a nonvolatile storage medium. The present invention also discloses an apparatus for adjusting a reference voltage. Thus, adjustment on the reference voltage of the chip is standardized and costs of the chip's application schemes are saved. A method and apparatus for obtaining a reference voltage are also provided, and thus stability of the circuit's working is improved and costs of the chip's applications are decreased.

Abstract: The present invention discloses a method for adjusting a reference voltage, including: decoding a default code configured in a reference voltage register in a chip to obtain an actual reference voltage; comparing the actual reference voltage with a benchmark value to obtain a deviation value between the two; configuring an adjustment code according to the deviation value; and, burning the adjustment code into a nonvolatile storage medium. The present invention also discloses an apparatus for adjusting a reference voltage. According to the method and apparatus for adjusting a reference voltage provided by embodiments of the present invention, the reference voltage need not be adjusted according to an external power supply's different application schemes. Thus, adjustment on the reference voltage of the chip is standardized and costs of the chip's application schemes are saved.