Abstract: An instruction buffer and a method of buffering instructions.

Abstract: A timing model is constructed using a timing view of a functional component of a circuit under consideration. This timing view uses one or more timing elements to replace timing determinant blocks of the actual circuitry for the purposes of timing analysis. These timing elements represent signal delays from point to point in the circuit and relative timing between signals in the circuit, and thus represent the important timing characteristics of the actual circuitry. After creating the timing view of the circuit, a cross-section of the circuit comprising the functional component is simulated to produce values for delays and relative timing between signals in the circuit. These values from the circuit simulation are then attached to the various timing elements in the timing view to create the timing model for the portion of the circuit represented by the timing view.