Patents by Inventor Zambri Samsudin

Zambri Samsudin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240098895
    Abstract: A bond pad connector to be disposed on a stretchable substrate and adapted to secure an electronic component thereon. The bond pad connector includes two spaced apart bond pads that are adapted to be disposed on the stretchable substrate to face each other. Each of the two bond pads is adapted to be connected to a respective conductive trace and includes: a stress relieve component that is adapted to be connected to the conductive trace, the stress relieve component being formed with a central hole; and an extension component extending from the stress relieve component and opposite to the conductive trace. The electronic component is secured onto the bond pad connector by attaching the electronic component to, for each of the bond pads, at least a part of the extension component.
    Type: Application
    Filed: July 19, 2023
    Publication date: March 21, 2024
    Applicant: Jabil Inc.
    Inventors: Lun Hao Tung, Lai Ming Lim, Zambri Samsudin
  • Publication number: 20240088544
    Abstract: A flexible composite substrate for a wearable antenna includes a fabric sheet and a single-layer dielectric film immersed into the fabric sheet. The single-layer dielectric film includes a dielectric resin matrix and a low dielectric loss material which is mixed with the dielectric resin matrix and which serves as a wireless functional dielectric interface material.
    Type: Application
    Filed: August 10, 2023
    Publication date: March 14, 2024
    Applicant: Jabil Inc.
    Inventors: Yen San Loh, Lai Ming Lim, Zambri Samsudin
  • Publication number: 20240040706
    Abstract: A rework patch for an electronic circuit includes a flexible patch body and at least two patch traces. The electronic circuit includes a substrate, at least two board traces formed on the substrate, and at least one defect portion within at least one of the board traces. The patch body is attached to the substrate to partially cover each of the board traces and to cover the defect portion. The patch traces are formed on the patch body. A pattern of the patch traces corresponds to a pattern of a portion of the board traces covered by the patch body.
    Type: Application
    Filed: May 18, 2023
    Publication date: February 1, 2024
    Applicant: Jabil Inc.
    Inventors: Muhammad Irsyad Bin Suhaimi, Lai Ming Lim, Zambri Samsudin
  • Publication number: 20220408565
    Abstract: An electronic circuit, comprising: an integrated substrate structure comprising one or more electrically conductive traces comprising plating on a laser-etched, non-conductive isolated portion of the integrated substrate structure defining each electrically conductive trace; one or more electrically conductive pads at one or more predetermined positions along the one or more electrically conductive traces; and an electrical component surface mounted to the at least one electrically conductive pad with interconnect and bonding material.
    Type: Application
    Filed: July 5, 2022
    Publication date: December 22, 2022
    Applicant: Jabil Inc.
    Inventors: Weiping (aka Jonathan) Wu, Mohd Yusuf Tura Ali, Zambri Samsudin
  • Publication number: 20200205295
    Abstract: A method for forming a circuit pattern on an integrated substrate structure includes providing an insulating surface which includes a pattern forming portion. An activation ink is deposited only on the pattern forming portion to form a non-conductive isolation layer. A first metal layer is formed on the non-conductive isolation layer by electroless plating. A patterned portion of the first metal layer is isolated from a remaining portion of the first metal layer to form the circuit pattern. A non-conductive masking layer is applied on the first metal layer. A second metal layer is formed on the non-conductive masking layer. A surface mount land pattern and pad configuration is determined. A solder mask layer is applied to the patterned portion. A protective layer is applied to protect pad areas not covered by the solder mask layer. An electrical component may then be mounted to the pad(s).
    Type: Application
    Filed: June 15, 2017
    Publication date: June 25, 2020
    Applicant: Jabil Inc.
    Inventors: Weiping (aka Jonathan) Wu, Mohd Yusuf Tura Ali, Zambri Samsudin