Patents by Inventor Zan-Chun Wei

Zan-Chun Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7638830
    Abstract: An MIM capacitor structure having a metal structure formed thereover is provided. A dielectric layer is disposed over the metal structure and a top layer is disposed over the dielectric layer. A capacitance trench is formed through the top layer and into the dielectric layer. Respective bottom electrodes are formed over the opposing side walls of the capacitance trench. A capacitance dielectric layer is disposed over the respective bottom electrodes, the bottom of the capacitance trench and the remaining top layer. Respective opposing initial via openings are formed adjacent the capacitance trench. Respective trench openings are formed above, continuous and contiguous with the lower portions of the respective opposing initial via openings and exposing portions of the underlying metal structure to form respective opposing dual damascene openings. Planarized metal portions disposed within the dual damascene openings and the capacitance trench form a top electrode.
    Type: Grant
    Filed: August 16, 2006
    Date of Patent: December 29, 2009
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ping-Yi Hsin, Zan-Chun Wei
  • Patent number: 7112504
    Abstract: As shown in FIG. 10, using photoresist capacitance trench masking portion 43 as a mask, the exposed portions 70, 72 of the patterned capacitance dielectric layer 32? between the respective initial via openings 36, 38 and the capacitance trench masking portion 43, the underlying twice patterned ARC 18? and the underlying twice patterned oxide layer 16? are etched down to a depth substantially equal to the bottom of the capacitance trench 25 to form respective trench openings 56, 58 contiguous and continuous with respective final via openings 52, 54, in turn forming respective dual damascene openings 57, 59. Final via openings 52, 54 expose underlying portions 78 of metal structure 12 and bottom electrodes 30?, 30?. Capacitance trench 25 includes sidewalls 50 formed of remaining portions of capacitance dielectric layer 32?.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: September 26, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ping-Yi Hsin, Zan-Chun Wei