Abstract: An apparatus includes a single sense pin connected to a line of a device connected to the apparatus, a gate pin configured to produce a gate signal to enable or disable a switch connected between the line of the device connected to the apparatus and a system ground, and control logic. The control logic is configured to at the single sense pin, determine a short between the device and the system ground, and, based upon the determination of the short, disable the switch.

Abstract: An IC incorporating a multiphase voltage converter with synchronized phase shift including a phase shift pin, a frequency select pin, a master clock pin, and a voltage regulator. The phase shift pin is coupled to a first voltage for a master mode or a first resistor for a slave mode. The frequency select pin is coupled to one of a second voltage and a second resistor. The master clock pin provides a master clock signal or receives an external clock signal. The IC provides the master clock signal at a frequency determined by the second resistor or otherwise at a default frequency. The voltage regulator operates in the slave mode at a phase shift relative to the external clock signal based on the first resistor and the second resistor or based on the first resistor and a default resistance if the second voltage is coupled.

Abstract: A power up clear (PUC) signal is generated, based on a value of a supply voltage VCC. A first circuit element (such as an n-channel MOSFET MN0) of a first conductivity type having a first characteristic threshold voltage, and a second circuit element (such as p-channel MOSFET MP0) of a second conductivity type having a second characteristic threshold voltage, are provided in a PUC signal generating circuit. A first circuit portion (including MN0, R0) is configured to provide a first comparison input signal VIN?, and a second circuit portion (including MP0, R1, R2, and, switchably, R3) is configured to provide a second comparison input signal VIN+. A comparator COMP compares the first and second comparison input signals VIN?, VIN+, to cause the PUC signal to transition to an active state when one of the first and second comparison signals crosses another of the first and second comparison signals, in response to an increasing magnitude of the supply voltage during power up.

Abstract: A system for controlling a plurality of load devices includes a high-side system operative to source current relative to at least two associated outputs. A low-side system is operative to sink current relative to a plurality of associated inputs. A control system controls the high-side system and the low-side system according to a multiplexing scheme that is operative to provide current to selected load devices of the plurality of load devices connected between the associated outputs and the associated inputs. The system can be implemented as an integrated circuit for driving the plurality of loads, which can include LED's.

Abstract: System for providing a switched regulator with an adjustable operating frequency range. A preferred embodiment comprises a voltage supply and a load, a switch and filter block (SFB) (such as the SFB 510), a comparator (such as the comparator 520), and a fixed off time logic (FOTL) (such as the FOTL 525). The comparator compares an output voltage with a reference voltage. When the output voltage is equal to or exceeds the reference voltage, the comparator asserts a value on a signal line to the FOTL. The FOTL then shuts down the SFB for a specified period of time. During the off time, the output voltage decays. After the specified period of time expires, the SFB is turned back on and the output voltage can recharge. The duration of time that the SFB remains on is a function of the supply voltage, thus permitting an adjustable operating frequency.