Abstract: In networks of interconnected router nodes for forwarding data traffic along a predetermined path of the network, a method of and system for imperceptibly upgrading router node software and the like without traffic interruption through a novel preparation of upgraded software in a router while that router continues to forward data under the control of its original software, and then swapping the upgraded software for the original software without disruption.

Abstract: A method of and operating architectural enhancement for combining photonic and data packet-based networks to be unified or integrated as a single device and with a common software control plane, enabling increased utilization of such combined networks and in particular of optical path data flow capacity.

Abstract: A method of and operating architectural enhancement for combining photonic and data packet-based networks to be unified or integrated as a single device and with a common software control plane, enabling increased utilization of such combined networks and in particular of optical path data flow capacity.

Abstract: A new data packet cell control method and apparatus, particularly, though not exclusively, for use with I/O packet cell source and destination resource networks using shared central multi-port internally cached dynamic random access memory (AMPIC DRAM), wherein a separate control path architecture is used, also incorporating AMPIC DRAM technology, to obviate problems with data traffic congestion resulting from significant I/O resource and for bandwidth requirement increases, and doing so while enabling scaling with data path, and retaining quality of service and increased multicast functionality, as well.

Abstract: A novel networking architecture and technique for transmitting both cells and packets or frames across a common switch fabric, effected, at least in part, by utilizing a common set of algorithms for the forwarding engine (the ingress side) and a common set of algorithms for the QoS management (the egress part) that are provided for each I/O module to process packet/cell information without impacting the correct operation of ATM switching and without transforming packets into cells for transfer across the switch fabric.

Abstract: A novel chip layout for a network wherein pluralities of I/O data ports are each connected to transmit/receive SRAM buffer banks operable under arbitration units to access pluralities of internally cached DRAM banks via internal busses to enable switching data connections amongst all data ports through the appropriate buffers, the chip layout having, data ports substantially symmetrically placed with each data port connected to each arbitration unit and each transmit/receive buffer bank, and with each data port enabled to write into any DRAM bank, with the connections being effected such that each data port is substantially symmetric with respect to DRAM bank, arbitration unit and transmit/receive buffer banks and busses; and with timing clocks centrally placed on the chip to minimize clock skew by symmetric clock distribution.

Abstract: A novel networking architecture and technique for reducing system latency caused, at least in part, by access contention for usage of common bus and memory facilities, wherein a separate data processing and queue management forwarding engine and queue manager are provided for each I/O module to process packet/cell control information and delivers queuing along a separate path that eliminates contention with other resources and is separate from the transfer of packet/cell data into and from the memory.