Patents by Inventor Zbigniew P. Sobczak

Zbigniew P. Sobczak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4885262
    Abstract: A process for chemically modifying spin-on-glass (SOG) for improved performance in semiconductor device fabrication is disclosed. To compensate for severe surface topographies associated with very large scale integration (VLSI) technology, a thicker non-etch back SOG process is utilized for forming a SOG layer over a chemical vapor deposition (CVD) layer. A single layer of SOG is formed over the CVD layer, providing planarizing coverage over formational or growth defects. The silylation of the SOG layer provides for the formation thicker single layers of SOG and significantly reduces the wet etching rate in diluted HF.
    Type: Grant
    Filed: March 8, 1989
    Date of Patent: December 5, 1989
    Assignee: Intel Corporation
    Inventors: Chiu H. Ting, Thomas G. Rucker, Zbigniew P. Sobczak
  • Patent number: 4604162
    Abstract: A process for fabricating silicon-on-insulator structures on semiconductor wafers and planarizing the topology of the patterns formed from the silicon. In the composite, the process provides for the formation of monocrystalline silicon islands electrically isolated by dielectric in substantially coplanar arrangement with surrounding dielectric. According to one practice of the process, substrate silicon islands are initially formed and capped, and thereafter used as masks to direct the anisotropic etch of the silicon substrate to regions between the islands. During the oxidation which follows, the capped and effectively elevated silicon islands are electrically isolated from the substrate by lateral oxidation through the silicon walls exposed during the preceding etch step. The capped regions, however, remain substantially unaffected during the oxidation. With the electrically isolated silicon island in place, a silicon dioxide layer and a planarizing polymer layer are deposited over the wafer.
    Type: Grant
    Filed: December 23, 1985
    Date of Patent: August 5, 1986
    Assignee: NCR Corporation
    Inventor: Zbigniew P. Sobczak
  • Patent number: 4576834
    Abstract: A streamlined process for forming a fully recessed, self-planarized dielectric isolation structure involves selectively depositing organosilicon material such as orthosilicate esters or siloxane resins in substrate trenches without build-up on adjacent substrate steps, which steps are coated with a non-wetting polymer material such as fluorocarbon compounds, then converting the organosilicon material to silicon oxide by heating at about 200.degree. C.-900.degree. C.
    Type: Grant
    Filed: May 20, 1985
    Date of Patent: March 18, 1986
    Assignee: NCR Corporation
    Inventor: Zbigniew P. Sobczak