Abstract: Systems and methods for identifying unbuildable part pairs in product data management (PDM) systems. A method includes receiving a product structure having a plurality of nodes with variant conditions. The method includes building, by the client PDM system, a variant condition forest (VCF) corresponding to the product structure and selecting a pair of nodes in the product structure. The method includes determining, using the VCF, whether the variant conditions of each of the selected nodes are satisfiable both separately and at the same time, and if not, marking the selected pair of nodes as unbuildable. The method includes adding the unbuildable pair of nodes to an unbuildable pairs list. The method includes performing a clearance analysis process on the product structure, without processing unbuildable pairs on the unbuildable pairs list, and storing the results of the clearance analysis process.

Abstract: Systems and methods for identifying unbuildable part pairs in product data management (PDM) systems. A method includes receiving a product structure having a plurality of nodes with variant conditions. The method includes building, by the client PDM system, a variant condition forest (VCF) corresponding to the product structure and selecting a pair of nodes in the product structure. The method includes determining, using the VCF, whether the variant conditions of each of the selected nodes are satisfiable both separately and at the same time, and if not, marking the selected pair of nodes as unbuildable. The method includes adding the unbuildable pair of nodes to an unbuildable pairs list. The method includes performing a clearance analysis process on the product structure, without processing unbuildable pairs on the unbuildable pairs list, and storing the results of the clearance analysis process.

Abstract: A method and apparatus for development and concurrent verification of digital designs including a combination of a microprocessor and discrete logic design blocks. The hardware/software design development and co-verification processing of digital designs is accelerated by placing the microprocessor in an FPGA device and logic circuits in an HDL simulator. The microprocessor and logic circuits are connected via a common bus and synchronization of both environments is achieved by using a simulator clock exclusively when both microprocessor and logic simulator need to communicate with each other. The system and method of the present invention provides a unique arrangement of a processor clocking scheme. An essential part of the invention is a clock switch responsive to the areas of RAM a processor is addressing and accordingly switching a clock signal to the processor from either a hardware clock generator or a software simulator.