Abstract: An asynchronous handshake signal is encoded in order to facilitate the transfer of the asynchronous handshake signal from a first network segment to a second network segment. On the first network segment, control signals and data signals are encoded as control symbols and data symbols, respectively. The control symbols and the data symbols are transferred from the first network segment to the second network segment across an interconnection medium. In order to send a handshake signal from the first network segment to the second network segment, the handshake signal on the first network segment is sampled. When the handshake signal on the first network segment is at a first signal level, a control symbol of encoded control signals is sent across the interconnection medium. When the handshake signal on the first network segment is at a second signal level, a data symbol of encoded data signals is sent across the interconnection medium.

Abstract: A method is used to perform arbitration between network devices connected to one of a first network segment and a second network segment, where the first network segment is connected to the second network segment by a long interconnection medium over an extended distance. When one or more network devices connected to the first network segment senses the network is free and desires control of the network for a data transfer, each of these network devices will assert a first network control signal. When the first network control signal is first asserted, this marks the beginning of an arbitration period for the first network segment. The first network control signal is forwarded to the second network segment. Upon the second network segment receiving the first network control signal, any arbitration currently in progress upon the second network segment is aborted.

Abstract: A programmable logic array is provided by symmetrically arraying drivers around the periphery of a substrate. These drivers are essentially OR/NOR gates having latched complementary outputs. The latched complementary outputs enable these logic gates to be implemented into flip-flop elements, and the complementary outputs allow these logic gates to be implemented into AND logic gates. Selectable feedback paths are also provided to add greater flexibility to the programmable logic array. Altogether, the symmetrical logic array provides a simple one-to-one representation of most logic designs to form a universal logic design board in the form of a random logic or programmable state machine.