Abstract: Methods and apparatus for formal verification. In one embodiment, values within a full model for formal verification are parameterized so that the parameters may be defined in order to perform verification on a reduced model. The number of states may then be reduced to allow formal verification on portions of a logic model of complex circuits such as microprocessors using present formal verification techniques. Preprocessor directives are used for multiple and conditional hardware description language generation for representation of a logic model of an integrated circuit, such as a microprocessor. Signals may also be freed from their associated circuitry, and placed into a non-deterministic state. Signals may also be set to a deterministic, designer-specified value. Associated circuitry may then be removed from the logic model for verification of a reduced model.