Patents by Inventor ZE-JIE LI

ZE-JIE LI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Packaging structure with embedded electronic components and method for manufacturing the same
    Patent number: 11864329
    Abstract: A method for manufacturing a fan-out chip packaging structure with decreased use of a crack-inducing hot-soldering process includes a first carrier plate with first and a second outer wiring layers. Two first conductive posts are formed on the first outer wiring layer, one end of each post is electrically connected to the first outer wiring layer. A receiving groove is formed between first conductive posts, and a sidewall of each post is surrounded by a first insulating layer. An embedded component is laid in the receiving groove and a second carrier plate is formed on the first insulating layer, wherein the second carrier plate carries third and fourth outer wiring layers. A first outer component is connected to the second outer wiring layer, and a second outer component is connected to the fourth outer wiring layer.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: January 2, 2024
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Chih-Chieh Fu, Yuan-Yu Lin, Ze-Jie Li
  • PACKAGING STRUCTURE WITH EMBEDDED ELECTRONIC COMPONENTS AND METHOD FOR MANUFACTURING THE SAME
    Publication number: 20230345643
    Abstract: A method for manufacturing a fan-out chip packaging structure with decreased use of a crack-inducing hot-soldering process includes a first carrier plate with first and a second outer wiring layers. Two first conductive posts are formed on the first outer wiring layer, one end of each post is electrically connected to the first outer wiring layer. A receiving groove is formed between first conductive posts, and a sidewall of each post is surrounded by a first insulating layer. An embedded component is laid in the receiving groove and a second carrier plate is formed on the first insulating layer, wherein the second carrier plate carries third and fourth outer wiring layers. A first outer component is connected to the second outer wiring layer, and a second outer component is connected to the fourth outer wiring layer.
    Type: Application
    Filed: May 25, 2022
    Publication date: October 26, 2023
    Inventors: CHIH-CHIEH FU, YUAN-YU LIN, ZE-JIE LI