Abstract: A chip packaging body includes a base circuit board, at least one chip unit, a plastic encapsulation layer, and multiple connection members. A chip of each chip unit is connected to a first surface of a corresponding metal substrate. The plastic encapsulation layer is disposed on the first surface of the base circuit board. An end of each connection member is connected to a corresponding electrode of the chip, and another end of each connection member extends to a first surface of the plastic encapsulation layer for exposure. The multiple connection members include a first connection member, an end of the first connection member is connected to a side surface of the metal substrate. Another end of the first connection member extends to a board edge area, and then vertically extends to a side of the plastic encapsulation layer away from the base circuit board for exposure.

Abstract: The present application provides a chip embedded package. The chip embedded package includes a base circuit board, a chip unit, an encapsulation layer, and a plurality of connecting members. The chip unit includes a metal substrate and a chip. A step defining a first surface and a second surface is formed on the metal substrate, and the chip is fixedly connected to the second surface. The first surface protrudes from the second surface, and the second surface extends to at least one side edge of the metal substrate. The connecting members include a first connecting member. An end of the first connecting member is connected to a first side of the chip, and another end of the first connecting member crosses the second surface to horizontally extend to a first side of the base circuit board, and extends to a board edge to be exposed.

Abstract: This invention introduces a kinetic energy recovery wind-wave integrated system for offshore wind power generation. The system consists of a semi-submersible platform equipped with a fan and an internal wave energy device. The device includes a shell housing a Power Take-Off (PTO) system, featuring a permanent magnet synchronous linear motor and an active controller. The motor's stator is fixed inside the shell, while its mover is connected to a counterweight block outside the stator, linked to the shell's top via a spring. Limiters are installed at both ends of the shell to restrict the counterweight block's movement. This system utilizes the wave energy device to absorb kinetic energy, which otherwise affects wind turbine stability, and converts it into usable electrical energy via the PTO system. This enhances the stability and safety of offshore wind turbine power generation.

Abstract: An inductor assembly and a manufacturing method for an inductor assembly are provided. The inductor assembly includes a circuit board, a magnetic component, and a winding wire. The circuit board defines a groove body, the magnetic component is embedded in the groove body, and the winding wire is arranged on the magnetic component, surrounds along a thickness direction of the magnetic component, and is electrically connected to the circuit board.

Abstract: A security calculation method and system for side channel resistance based on data marking is used to defend against a microarchitectural side-channel attack (SCA), particularly a transient-execution attack. The method is data-centric, and based on data marking. Through the data marking (page table entry (PTE) marking and instruction marking), and a delayed update mechanism dependent on the data marking, the method ensures that any subsequent instructions dependent on a memory-sensitive instruction are not executed in speculative execution, thereby preventing confidential data from being leaked when a conditional branch outcome is unknown, effectively resisting the SCA, improving the security, and minimizing the impact on central processing unit (CPU) performance.

Abstract: A high-throughput confidential computing method and system based on a RISC-V architecture are provided. The method includes: S1, acquiring a hardware device tree configuration file to classify each physical resource into a normal partition or a security partition; S2, loading a security manager; S3, mapping memory resources in the normal and security partitions to the normal and security domains, respectively; registering CPU resources in the normal and security partitions to the normal and security domains, respectively; and registering an interrupt handler function; S4, linking an image file of a security file system with a security kernel file to generate an operating system image of the security domain; S5, reading the operating system image, and loading the same to a memory address of the security domain; and S6, executing the initialization of the security domain according to an interrupt request from the normal domain.

Abstract: A security calculation method and system for side channel resistance based on data marking is used to defend against a microarchitectural side-channel attack (SCA), particularly a transient-execution attack. The method is data-centric, and based on data marking. Through the data marking (page table entry (PTE) marking and instruction marking), and a delayed update mechanism dependent on the data marking, the method ensures that any subsequent instructions dependent on a memory-sensitive instruction are not executed in speculative execution, thereby preventing confidential data from being leaked when a conditional branch outcome is unknown, effectively resisting the SCA, improving the security, and minimizing the impact on central processing unit (CPU) performance.

Abstract: A high-throughput confidential computing method and system based on a RISC-V architecture are provided. The method includes: S1, acquiring a hardware device tree configuration file to classify each physical resource into a normal partition or a security partition; S2, loading a security manager; S3, mapping memory resources in the normal and security partitions to the normal and security domains, respectively; registering CPU resources in the normal and security partitions to the normal and security domains, respectively; and registering an interrupt handler function; S4, linking an image file of a security file system with a security kernel file to generate an operating system image of the security domain; S5, reading the operating system image, and loading the same to a memory address of the security domain; and S6, executing the initialization of the security domain according to an interrupt request from the normal domain.

Abstract: Provided are an antenna apparatus and an electronic device. A first coupling gap is formed between one end of a second radiator and a first radiator, and the other end of the second radiator is provided with a first ground terminal. One end of a third radiator is connected to the first ground terminal, and the other end thereof extends in a direction away from the second radiator. The third radiator is provided with a second ground terminal spaced apart from the first ground terminal. At least part of the first radiator and the second radiator jointly generate a first resonance. A part of the third radiator located on a side of the second ground terminal away from the first ground terminal generates a second resonance.

Abstract: An antenna assembly and an electronic device are provided. The antenna assembly includes a substrate, a radiating patch, and a matching structure. The radiating patch is disposed on the substrate. The matching structure is configured to be electrically connected with a radio frequency (RF) signal circuit at one end of the matching structure, and the matching structure is provided with a first coupling piece at the other end of the matching structure. The first coupling piece is in capacitive coupling with the radiating patch. The first coupling piece is configured to feed a RF signal generated by the RF signal circuit into the radiating patch, to excite the radiating patch to generate multiple resonant modes. At least one resonant mode in the multiple resonant modes is generated by the capacitive coupling between the first coupling piece and the radiating patch.

Abstract: This invention introduces a kinetic energy recovery wind-wave integrated system for offshore wind power generation. The system consists of a semi-submersible platform equipped with a fan and an internal wave energy device. The device includes a shell housing a Power Take-Off (PTO) system, featuring a permanent magnet synchronous linear motor and an active controller. The motor's stator is fixed inside the shell, while its mover is connected to a counterweight block outside the stator, linked to the shell's top via a spring. Limiters are installed at both ends of the shell to restrict the counterweight block's movement. This system utilizes the wave energy device to absorb kinetic energy, which otherwise affects wind turbine stability, and converts it into usable electrical energy via the PTO system. This enhances the stability and safety of offshore wind turbine power generation.

Abstract: An antenna assembly and an electronic device are provided. A first antenna element includes a first radiator, a ground branch, and a first signal source. A joint of a first radiating branch and a second radiating branch is a first feed point. The first signal source is electrically connected to the first feed point. The ground branch, the first signal source, and the first radiating branch form a first sub-antenna. The ground branch, the first signal source, and the second radiating branch form a second sub-antenna. The first sub-antenna is configured to transmit/receive electromagnetic wave signals of a first target band under excitation of the first signal source. The second sub-antenna is configured to transmit/receive electromagnetic wave signals of a second target band under excitation of the first signal source. The first target band at least partially overlaps with the second target band.

Abstract: An antenna assembly and an electronic device are provided. The antenna assembly includes a substrate, a radiating patch, and a matching structure. The radiating patch is disposed on the substrate. The matching structure is configured to be electrically connected with a radio frequency (RF) signal circuit at one end of the matching structure, and the matching structure is provided with a first coupling piece at the other end of the matching structure. The first coupling piece is in capacitive coupling with the radiating patch. The first coupling piece is configured to feed a RF signal generated by the RF signal circuit into the radiating patch, to excite the radiating patch to generate multiple resonant modes. At least one resonant mode in the multiple resonant modes is generated by the capacitive coupling between the first coupling piece and the radiating patch.

Abstract: Provided are an antenna apparatus and an electronic device. A first coupling gap is formed between one end of a second radiator and a first radiator, and the other end of the second radiator is provided with a first ground terminal. One end of a third radiator is connected to the first ground terminal, and the other end thereof extends in a direction away from the second radiator. The third radiator is provided with a second ground terminal spaced apart from the first ground terminal. At least part of the first radiator and the second radiator jointly generate a first resonance. A part of the third radiator located on a side of the second ground terminal away from the first ground terminal generates a second resonance.

Abstract: An inductor assembly and a manufacturing method for an inductor assembly are provided. The inductor assembly includes a circuit board, a magnetic component, and a winding wire.

Abstract: The invention, which relates to the technical field of circuit boards, specifically discloses a method for manufacturing an embedded circuit board, an embedded circuit board, and an application thereof. The method includes: providing a substrate, wherein an electronic component is embedded in the substrate, a pad is arranged on a side surface of the electronic component, and an end surface of the pad is flush with a same side surface of the substrate; forming a metallic layer on a side surface of the substrate adjacent to the pad by sputtering, evaporation, electroplating or chemical vapor deposition; and patterning the metallic layer to obtain a circuit board covered with the metallic layer on the pad, wherein the metallic layer on the pad protrudes beyond the same side surface of the substrate.

Abstract: The present disclosure provides a circuit board and a method for manufacturing the circuit board. The circuit board may include: a base board, an embedded component, and an attached component. The base board may define a groove, the embedded component can be disposed in the groove. The attached component can be attached to at least one surface of the base board and connected to the embedded component.

Abstract: The invention, which relates to the technical field of inductance embedding, specifically discloses an embedded circuit board. The embedded circuit board includes: at least layer of sub-body, where preset positions of the sub-bodies are provided with through slots; and an inductance element embedded within the slots and configured to be spaced apart from sidewalls of the slots. In the above manner, it is possible to make the embedded circuit board of the present application structurally compact, highly integrated, widely applicable, and safe and reliable.

Abstract: The present application provides a circuit board and a manufacturing method therefor. The circuit board includes: a core board, at least one chip, a first circuit layer, and a first insulating layer. A groove body is formed on the core board. The chip is provided in the groove body. The chip is provided with a first lead-out terminal. The first circuit layer is provided on at least one side of the core board. The first insulating layer is provided between the core board and the first circuit layer. The first lead-out terminal passes through the first insulating layer and is connected to the first circuit layer, so that the chip is electrically connected to the first circuit layer. Thus, the wiring between the chip and the circuit is more flexible.

Abstract: A circuit board is provided, including: a core board, defining a plurality of slots, the plurality of slots including a plurality of first sub-slots and a plurality of second sub-slots disposed beneath the first sub-slots. Each of the second sub-slots is located beneath a corresponding first sub-slot of the first sub-slots; and a plurality of chip assemblies, arranged in the slots and including a plurality of first chips located in the first sub-slots and a plurality of second chips located in the second sub-slots. Each of the first chips is connected in series with one of the second chips at a corresponding position to form a plurality of chipsets; the chipsets are connected in parallel with each other; an end of the chipsets is connected to a first power signal layer, and the other end of the plurality of chipsets is connected to a ground layer.