Patents by Inventor Zeeshan Sarwar

Zeeshan Sarwar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Power gated communication controller
    Patent number: 10394309
    Abstract: A method includes detecting a communication event over a communication bus 130 coupled to a device, and in response to detecting the communication event, deactivating a module of the device. The method may further include sending a data throttle packet over the communication bus 130 while the deactivated module reactivates.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Tiong Hong Teoh, Zeeshan Sarwar
  • POWER GATED COMMUNICATION CONTROLLER
    Publication number: 20170115724
    Abstract: A method includes detecting a communication event over a communication bus 130 coupled to a device, and in response to detecting the communication event, deactivating a module of the device. The method may further include sending a data throttle packet over the communication bus 130 while the deactivated module reactivates.
    Type: Application
    Filed: December 30, 2016
    Publication date: April 27, 2017
    Inventors: Tiong Hong Teoh, Zeeshan Sarwar
  • POWER GATED COMMUNICATION CONTROLLER
    Publication number: 20170017289
    Abstract: A method includes detecting a communication event over a communication bus 130 coupled to a device, and in response to detecting the communication event, deactivating a module of the device. The method may further include sending a data throttle packet over the communication bus 130 while the deactivated module reactivates.
    Type: Application
    Filed: September 29, 2016
    Publication date: January 19, 2017
    Inventors: Tiong Hong Teoh, Zeeshan Sarwar
  • Power gated communication controller
    Patent number: 9489032
    Abstract: A method includes detecting a communication event over a communication bus 130 coupled to a device, and in response to detecting the communication event, deactivating a module of the device. The method may further include sending a data throttle packet over the communication bus 130 while the deactivated module reactivates.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: November 8, 2016
    Assignee: INTEL CORPORATION
    Inventors: Tiong Hong Teoh, Zeeshan Sarwar
  • Inter-chip communications with link layer interface and protocol adaptor
    Patent number: 9280510
    Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: March 8, 2016
    Assignee: Intel Corporation
    Inventors: Sridharan Ranganathan, David J. Harriman, Anoop Mukker, Satheesh Chellappan, Karthi R. Vadivelu, Shalini Sharma, Zeeshan Sarwar
  • SUPERSPEED INTER-CHIP INTERFACE
    Publication number: 20150134866
    Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.
    Type: Application
    Filed: January 20, 2015
    Publication date: May 14, 2015
    Inventors: Sridharan Ranganathan, David J. Harriman, Anoop Mukker, Satheesh Chellappan, Karthi R. Vadivelu, Shalini Sharma, Zeeshan Sarwar
  • Superspeed inter-chip interface
    Patent number: 8972646
    Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: March 3, 2015
    Assignee: Intel Corporation
    Inventors: Sridharan Ranganathan, David J. Harriman, Anoop Mukker, Satheesh Chellappan, Karthi R. Vadivelu, Shalini Sharma, Zeeshan Sarwar
  • POWER GATED COMMUNICATION CONTROLLER
    Publication number: 20140068287
    Abstract: A method includes detecting a communication event over a communication bus 130 coupled to a device, and in response to detecting the communication event, deactivating a module of the device. The method may further include sending a data throttle packet over the communication bus 130 while the deactivated module reactivates.
    Type: Application
    Filed: December 19, 2012
    Publication date: March 6, 2014
    Inventors: Tioag Hong Teoh, Zeeshan Sarwar
  • SUPERSPEED INTER-CHIP COMMUNICATIONS
    Publication number: 20130262731
    Abstract: An interface for low power, high bandwidth communications between units in a device in provided herein. The interface comprises a USB 3.0 system interface and a SuperSpeed inter-chip (SSIC) protocol adaptor configured to facilitate communications between the USB 3.0 system interface and an M-PHY interface.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Sridharan Ranganathan, David J. Harriman, Anoop Mukker, Satheesh Chellappan, Karthi R. Vadivelu, Shalini Sharma, Zeeshan Sarwar
  • COMMUNICATIVELY COUPLING, AT LEAST IN PART, SERIAL BUS CONTROLLER TO AT LEAST ONE SERIAL BUS DEVICE
    Publication number: 20120054402
    Abstract: An embodiment may include circuitry to communicatively couple, at least in part, a serial bus controller to at least one serial bus device. The circuitry may have at least one port to be communicatively coupled to the at least one device. The circuitry may route, at least in part, at least one packet issued, at least in part, from the controller to the at least one device via the at least one port based at least in part upon at least one address. The circuitry may associate, at least in part, the at least one address with the at least one port. The at least one address may be assigned, at least in part, to the at least one device by the controller as a result, at least in part, of enumeration, at least in part, of the at least one device by the controller.
    Type: Application
    Filed: August 27, 2010
    Publication date: March 1, 2012
    Inventors: Dhinesh Sasidaran, Asad Azam, Zeeshan Sarwar