Abstract: Systems and method are provided herein which enable dual-protocol femtocell-less communications. A communication router is arranged to communicate with one or more user equipment (UEs) over a non-cellular protocol and further communicate via a communication link with a cellular communication network operating in a cellular communication protocol. The UEs or the communication router comprise a femtoless client module which mediates non-cellular communication between the UEs and the celellular network. The UEs are arranged to communicate with base stations connected to the cellular communication network both over the cellular communication protocol as well as over the non-cellular communication protocol via the communication router. The UEs are configured to switch between non-cellular and cellular communication, based on predefined criteria. In the former case, cellular air interface is avoided.

Abstract: A novel distributed base station architecture having a multiplexer. The base station transmits base station controller interface data over an internet protocol (IP) communication channel. The multiplexer receives the data and combines it with other base station controller interface data to form a single base station controller interface data signal.

Abstract: A method for privacy management includes providing a linked collection of interactive resources through which a user is able to exchange information with an enterprise that provides the resources, and assigning respective, non-uniform privacy policies to at least some of the resources regarding use of the information that is exchanged through the resources. The user, accessing a given one of the resources, is provided with the respective privacy policy for that resource. At least a portion of the information that is associated with the given one of the resources is exchanged with the user subject to the provided privacy policy.

Abstract: A method for privacy management includes providing a linked collection of interactive resources through which a user is able to exchange information with an enterprise that provides the resources, and assigning respective, non-uniform privacy policies to at least some of the resources regarding use of the information that is exchanged through the resources. The user, accessing a given one of the resources, is provided with the respective privacy policy for that resource. At least a portion of the information that is associated with the given one of the resources is exchanged with the user subject to the provided privacy policy.

Abstract: A method for controlling an exchange of information between a first party and a second party includes receiving from the first party a set of one or more privacy preferences, indicating restrictions to be placed on use of specified items of the information to be disclosed by the first party, and receiving from the second party a description of a privacy policy, indicating undertakings by the second party with regard to restricting the use of the specified items of the information. The compatibility of the privacy preferences with the privacy policy is assessed. If the privacy preferences and the privacy policy are found to be incompatible, a negotiation is brokered with at least one of the first and the second parties so as to bring the privacy preferences and the privacy policy into mutual compatibility. The information is provided from the first party to the second party only when the privacy preferences and the privacy policy are found to be compatible.

Abstract: A method for modeling complementary metal oxide semiconductor (CMOS) combinatorial logic circuits by Boolean gates taking into account circuit behavior effects due to charge storing and static hazards. Models are developed for both the faultless and faulty operation of each circuit. According to a further aspect of the invention, these models are used in a simulation procedure to evaluate the fault coverage of a large scale integrated circuit design built using a plurality of these circuits. In the evaluation procedure the faulty model is used only for a particular circuit whose failure performance is being tested and the faultless model is utilized for all other circuits. This procedure is continued until all of the individual gate circuits have been evaluated.

Abstract: A shift register latch (SRL) arrangement for testing a combinational logic circuit, producing true and complement outputs in nature, has two clocked DC latches and additional circuitry for providing an input to the second latch. Clock signal trains and an extra TEST signal are used to control the SRL arrangement in different modes. In a first mode, one of the outputs from the combinational logic circuit is latched into the first latch and provided to a succeeding combinational logic circuit. In a second mode, a plurality of the SRL arrangements are interconnected together to form a shift register chain so that each latch acts as one position of the shift register chain. Further, in a third mode, the true and complement outputs of the combinational logic circuit are exclusive ORed and its result is latched into the second latch. During the third mode, output of the first latch is prevented from being latched into the second latch.