Abstract: An artificial neuron network and corresponding neuron units are described and corresponding neuron units. The neuron network comprises a plurality of two or more layers of artificial neuron units. The layers of artificial neuron units are configured for communicating between them via an arrangement of two or more optical waveguide (optical fibers). The arrangement of two or more optical waveguides are configured with predetermined coupling between the two or more waveguides, thereby providing cross communication between neuron units of said two or more layers.

Abstract: An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

Abstract: An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

Abstract: An input/output (I/O) sensor for a multi-IC module. The I/O sensor includes: delay circuitry, configured to receive a data signal from an interconnected part of an IC of the multi-IC module and to generate a delayed data signal, the delay circuitry including an adjustable delay-line configured to delay an input signal by a set time duration; a comparison circuit, configured to generate a comparison signal by comparing the data signal with the delayed data signal; and processing logic, configured to set the time duration of the adjustable delay-line and, based on the comparison signal, identify a margin measurement of the data signal for determining an interconnect quality parameter.

Abstract: The present invention provides a handheld USB Cup for use in collection of a fluidic body sample, comprising ad receptacle comprising side surfaces, a bottom plate and a sensor assembly, the sensor assembly comprising at least one sensor and a slave circuitry; said sensor assembly is permanently affixed to said side surfaces or said bottom plate. The receptacle is capable of maintaining the fluidic body sample for a sufficient time period in the vicinity of the sensor thereby the sensor is operative to provide continuous measurement of an electric, chemical or physical property of the urine. The slave circuitry responds to the electric, chemical or physical property of the fluidic body sample received from the sensor and is configured and operable to electronically communicate the measurement of the electric, chemical or physical property of the fluidic body sample to an external processing master unit.

Abstract: A method for data storage in a memory that includes a plurality of analog memory cells includes estimating respective achievable storage capacities of the analog memory cells. The memory cells are assigned respective storage configurations defining quantities of data to be stored in the memory cells based on the estimated achievable capacities. The data is stored in the memory cells in accordance with the respective assigned storage configurations. The achievable storage capacities of the analog memory cells are re-estimated after the memory has been installed in a host system and used for storing the data in the host system. The storage configurations are modified responsively to the re-estimated achievable capacities.

Abstract: A method for data storage in a memory that includes a plurality of analog memory cells includes estimating respective achievable storage capacities of the analog memory cells. The memory cells are assigned respective storage configurations defining quantities of data to be stored in the memory cells based on the estimated achievable capacities. The data is stored in the memory cells in accordance with the respective assigned storage configurations. The achievable storage capacities of the analog memory cells are re-estimated after the memory has been installed in a host system and used for storing the data in the host system. The storage configurations are modified responsively to the re-estimated achievable capacities.

Abstract: A method for data storage in a memory (28) that includes a plurality of analog memory cells (32) includes estimating respective achievable storage capacities of the analog memory cells. The memory cells are assigned respective storage configurations defining quantities of data to be stored in the memory cells based on the estimated achievable capacities. The data is stored in the memory cells in accordance with the respective assigned storage configurations. The achievable storage capacities of the analog memory cells are re-estimated after the memory has been installed in a host system and used for storing the data in the host system. The storage configurations are modified responsively to the re-estimated achievable capacities.

Abstract: Method and apparatus for automatically controlling the operation of a DC power enhancement circuitry connected to an RF power amplifier (PA) that operates at various input signal levels, according to which the instantaneous magnitude of the input signal is sensed and the instantaneous magnitude and its highest (lowest) peak are stored. For the time period during which the peak remains the highest (lowest) peak, the desired dynamic range of the power amplifier is determined according to the peak and a corresponding threshold level and the gain of the enhancement circuitry are determined according for that time period. Whenever the magnitude exceeds the corresponding threshold level, the enhancement circuitry provides to the power amplifier a level of DC power enhancement required for maintaining the output power of the power amplifier within the output dynamic range.

Abstract: The present invention provides a handheld USB Cup for use in collection of a fluidic body sample, comprising a receptacle comprising side surfaces, a bottom plate and a sensor assembly, the sensor assembly comprising at least one sensor and a slave circuitry; said sensor assembly is permanently affixed to said side surfaces or said bottom plate. The receptacle is capable of maintaining the fluidic body sample for a sufficient time period in the vicinity of the sensor thereby the sensor is operative to provide continuous measurement of an electric, chemical or physical property of the urine. The slave circuitry responds to the electric, chemical or physical property of the fluidic body sample received from the sensor and is configured and operable to electronically communicate the measurement of the electric, chemical or physical property of the fluidic body sample to an external processing master unit.

Abstract: A method for operating a memory that includes multiple analog memory cells includes storing data in the memory by writing first storage values to the cells, so as to cause the cells to hold respective electrical charge levels. After storing the data, second storage values are read from at least some of the cells, including at least one interfered cell that belongs to a group of cells. A Back Pattern Dependency (BPD) distortion caused by the electrical charge levels of one or more interfering cells in the group to at least one of the second storage values read from the at least one interfered cell is detected and canceled. The second storage values, including the at least one of the second storage values in which the BPD distortion was canceled, are processed so as to reconstruct the data.

Abstract: A method for data storage in a memory (28) that includes a plurality of analog memory cells (32) includes estimating respective achievable storage capacities of the analog memory cells. The memory cells are assigned respective storage configurations defining quantities of data to be stored in the memory cells based on the estimated achievable capacities. The data is stored in the memory cells in accordance with the respective assigned storage configurations. The achievable storage capacities of the analog memory cells are re-estimated after the memory has been installed in a host system and used for storing the data in the host system. The storage configurations are modified responsively to the re-estimated achievable capacities.

Abstract: Method and apparatus for automatically controlling the operation of a DC power enhancement circuitry connected to an RF power amplifier (PA) that operates at various input signal levels, according to which the instantaneous magnitude of the input signal is sensed and the instantaneous magnitude and its highest (lowest) peak are stored. For the time period during which the peak remains the highest (lowest) peak, the desired dynamic range of the power amplifier is determined according to the peak and a corresponding threshold level and the gain of the enhancement circuitry are determined according for that time period. Whenever the magnitude exceeds the corresponding threshold level, the enhancement circuitry provides to the power amplifier a level of DC power enhancement required for maintaining the output power of the power amplifier within the output dynamic range.

Abstract: A method for storing data in a memory that includes a plurality of analog memory cells includes mapping the data to programming values, which are selected from a set of nominal programming values. The set of nominal programming values includes at least a first nominal programming value and a second nominal programming value, which is higher than the first nominal programming value. A part of the data is stored in the analog memory cells by programming at least a first group of the cells using the first nominal programming value. A statistical characteristic of the first group of the cells is measured after programming the first group of the cells using the first nominal programming value. The second nominal programming value is modified responsively to the statistical characteristic, and at least a second group of the cells is programmed using the modified second nominal programming value.

Abstract: A method of operating an electronic device includes storing a first plurality of bits of digital information in a memory using a first number of memory cells in parallel. The first plurality of bits of digital information are for operating the device when operating parameters are not within a nominal range. The method also includes storing a second plurality of bits of digital information in the memory using a second number of memory cells in parallel. The second plurality of bits of digital information are for operating the device when operating parameters are within a nominal range.

Abstract: A method for operating a memory that includes multiple analog memory cells includes storing data in the memory by writing first storage values to the cells, so as to cause the cells to hold respective electrical charge levels. After storing the data, second storage values are read from at least some of the cells, including at least one interfered cell that belongs to a group of cells. A Back Pattern Dependency (BPD) distortion caused by the electrical charge levels of one or more interfering cells in the group to at least one of the second storage values read from the at least one interfered cell is detected and canceled. The second storage values, including the at least one of the second storage values in which the BPD distortion was canceled, are processed so as to reconstruct the data.

Abstract: Embodiments of the invention relate to non-volatile memory devices and their methods of manufacture. Embodiments comprise an array of non-volatile memory cells, the array comprising a multiplicity of array columns having at least one redundant column of non-volatile memory cells adapted to replace a defective array column, a column decoder, and a column redundancy unit. The column decoder is adapted to receive an address of a memory cell to which data is to be written or from which data is to be read. The column redundancy unit is adapted to decide whether the decoded address is to be written to or read from an array from or a redundant column. The data required by the column redundancy unit is stored in a column redundancy memory, which is connected to the column redundancy unit by means of a dedicated column redundancy bus.

Abstract: A method for storing data in a memory that includes a plurality of analog memory cells includes mapping the data to programming values, which are selected from a set of nominal programming values. The set of nominal programming values includes at least a first nominal programming value and a second nominal programming value, which is higher than the first nominal programming value. A part of the data is stored in the analog memory cells by programming at least a first group of the cells using the first nominal programming value. A statistical characteristic of the first group of the cells is measured after programming the first group of the cells using the first nominal programming value. The second nominal programming value is modified responsively to the statistical characteristic, and at least a second group of the cells is programmed using the modified second nominal programming value.

Abstract: A memory device is presented that includes a plurality of memory cells coupled to a bitline, and two or more pre-charging circuits coupled to the bitline. Each of the pre-charging circuits is operable to supply a pre-charge voltage to the bitline, thereby reducing the effective R-C time constant of the bitline compared with the conventional approach in which only a single pre-charging circuit is employed.

Abstract: A method of operating an electronic device includes storing a first plurality of bits of digital information in a memory using a first number of memory cells in parallel. The first plurality of bits of digital information are for operating the device when operating parameters are not within a nominal range. The method also includes storing a second plurality of bits of digital information in the memory using a second number of memory cells in parallel. The second plurality of bits of digital information are for operating the device when operating parameters are within a nominal range.