Patents by Inventor Zeev Kirshenbaum

Zeev Kirshenbaum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11719749
    Abstract: A computer implemented method may include executing a first simulation test for testing a device under test (DUT) and a corresponding test environment; saving a snapshot image of the DUT and of the corresponding test environment upon completion of initialization actions included in the first simulation test to configure the DUT; compiling a DUT part of a second simulation test into the saved snapshot image of the DUT to obtain a restore image for the DUT; loading the restore image of the DUT and restoring the snapshot image of the test environment; loading a test environment part of the second simulation test; and executing the second simulation test on the DUT and corresponding test environment.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: August 8, 2023
    Assignee: CADENCE DESIGN SYSTEMS, INC.
    Inventors: Tirumala Surya Prasad Annepu, Shai Fuss, Zeev Kirshenbaum