Abstract: A method for parallel decoding which is applied to a processor including a first decoder cluster and a second decoder cluster, the second decoder cluster being provided with at least one shared decoder shared by the first decoder cluster. In the method, if a quantity of a plurality of instructions is greater than a quantity of decoders in the first decoder cluster, the processor assigns, from the plurality of instructions, first instructions with a quantity corresponding to the quantity decoders of the first decoder cluster to a decoder in the first decoder cluster for decoding, and the processor assigns, from the plurality of instructions, at least one second instruction other than the first instructions to the at least one shared decoder for decoding. The processor then writes micro-ops obtained by decoding the first instructions and micro-ops obtained by decoding the at least one second instruction into a first micro-op queue.

Abstract: A decoding method of a simultaneously multi-threading processor, a processor, and a chip are provided. The method includes: fetching an instruction stream according to an instruction fetching request; segmenting the instruction stream which is fetched in response to the simultaneously multi-threading processor being in a single-threaded mode; allocating the instructions at split positions as boundaries of switching instructions queues, wherein the plurality of target instruction queues comprise instruction queues corresponding to active threads and instruction queues corresponding to inactive threads; and decoding the instructions in the plurality of target instruction queues by using a plurality of decoder groups to obtain micro-ops obtained after decoding by the decoder groups. The embodiments of the present disclosure can improve the decoding efficiency of a multi-thread processor while being compatible with multiple thread modes.

Abstract: A decoding method of a simultaneously multi-threading processor, a processor, and a chip are provided. The method includes: fetching an instruction stream according to an instruction fetching request; segmenting the instruction stream which is fetched in response to the simultaneously multi-threading processor being in a single-threaded mode; allocating the instructions at split positions as boundaries of switching instructions queues, wherein the plurality of target instruction queues comprise instruction queues corresponding to active threads and instruction queues corresponding to inactive threads; and decoding the instructions in the plurality of target instruction queues by using a plurality of decoder groups to obtain micro-ops obtained after decoding by the decoder groups. The embodiments of the present disclosure can improve the decoding efficiency of a multi-thread processor while being compatible with multiple thread modes.

Abstract: Embodiments of the present disclosure provide a method for parallel decoding which is applied to a processor including at least a first decoder cluster and a second decoder cluster, the second decoder cluster being provided with at least one shared decoder shared by the first decoder cluster. In the method if a quantity of a plurality of instructions is greater than a quantity of decoders in the first decoder cluster, assigning first instructions with a quantity corresponding to the quantity decoders of the first decoder cluster in the plurality of instructions to a decoder in the first decoder cluster for decoding, and assigning second instructions other than the first instructions in the plurality of instructions to the at least one shared decoder for decoding; writing, micro-ops obtained by decoding the first instructions and micro-ops obtained by decoding the second instructions into the first micro-op queue.

Abstract: Embodiments of the present disclosure provide a decoding method, a processor, a chip, and an electronic device. The method includes: generating an instruction fetch request carrying at least one switching flag, in which the switch tag at least indicates an instruction position for performing decoder group switch; acquiring an instruction stream fetched by the instruction fetching request in response to a micro-op being obtained as decoded by decoder group, and determining the instruction position for performing decoder group switch in the instruction stream according to the switch tag carried by the instruction fetching request; allocating the instruction steam to a plurality of decoder groups for parallel decoding according to the instruction position; and attaching the switch tag to a target micro-op obtained by decoding a targe instruction, in which the target instruction is an instruction corresponding to the instruction position.

Abstract: In a method for accessing an extended memory, after receiving a first memory access request from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

Abstract: A cache management method for a computing device, a cache controller, a processor and a processor readable storage medium are disclosed. The cache management method for the computing device includes classifying a workload on a cache based on a cache architecture of the computing device, characteristics of a cache level of the cache and a difference in the workload on the cache, and configuring a priority for the classified workload; and allocating a cache resource and performing cache management according to the configured priority.

Abstract: Disclosed in embodiments of the present disclosure are a processor and an instruction operation method. The method includes obtaining criticality information of an instruction, wherein the criticality information of the instruction indicates importance degree of the instructions in a running process of a program; determining an operation sequence of the instruction based on the criticality information; and performing operations for the instruction based on the determined operation sequence of the instruction.

Abstract: Disclosed in embodiments of the present disclosure are a processor and an instruction operation method. The method includes obtaining criticality information of an instruction, wherein the criticality information of the instruction indicates importance degree of the instructions in a running process of a program; determining an operation sequence of the instruction based on the criticality information; and performing operations for the instruction based on the determined operation sequence of the instruction.

Abstract: A cache management method for a computing device, a cache controller, a processor and a processor readable storage medium are disclosed. The cache management method for the computing device includes classifying a workload on a cache based on a cache architecture of the computing device, characteristics of a cache level of the cache and a difference in the workload on the cache, and configuring a priority for the classified workload; and allocating a cache resource and performing cache management according to the configured priority.

Abstract: In a method for accessing an extended memory, after receiving a first memory access request from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

Abstract: A memory management method and a device, where the method includes: receiving a memory access request, where the memory access request carries a virtual address; determining a page fault type of the virtual address if finding, in a translation lookaside buffer TLB and a memory, no page table entry corresponding to the virtual address; allocating a corresponding page to the virtual address if the page fault type of the virtual address is a blank-page-caused page fault, where the blank-page-caused page fault means that no corresponding page is allocated to the virtual address; and updating the page table entry corresponding to the virtual address to the memory and the TLB. The memory manager does not generate a page fault when a blank-page-caused page fault occurs, but allocates a corresponding page to the virtual address. Therefore, a quantity of occurrences of the page fault is reduced, thereby improving memory management efficiency.

Abstract: A method for accessing an extended memory, a device, and a system are disclosed. According to the method, after receiving a first memory access requests from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

Abstract: A memory management method and device are disclosed. The method includes: managing, by a storage management device, a memory; and when determining that a page table does not include a virtual address carried in a fetch request, managing, by the memory management device, the memory. When determining that the virtual address is valid, the memory management device applies for a blank page. The memory management device is located in a memory controller.

Abstract: A method for refreshing a dynamic random access memory DRAM and a computer system are provided. When an address of a refresh unit in a DRAM and refresh information of the refresh unit are acquired, the address of the refresh unit and the refresh information of the refresh unit are encapsulated as a DRAM access request, where the refresh unit is storage space on which one time of refresh is performed in the DRAM, and the refresh information of the refresh unit includes a refresh cycle of the refresh unit. Then, the address and the refresh information of the refresh unit are written into refresh data space using the DRAM access request, where the refresh data space is storage space that is preset in the DRAM and that is used for storing an address of at least one refresh unit and refresh information of the at least one refresh unit.

Abstract: A mapping processing method and apparatus for a cache address, where the method includes acquiring a physical address corresponding to an access address sent by a processing core, where the physical address includes a physical page number (PPN) and a page offset, mapping the physical address to a Cache address, where the Cache address includes a Cache set index 1, a Cache tag, a Cache set index 2, and a Cache block offset in sequence, where the Cache set index 1 with a high-order bit and the Cache set index 2 with a low-order bit together form a Cache set index, and the Cache set index 1 falls within a range of the PPN. Some bits of a PPN of a huge page PPN are mapped to a set index of a Cache so that the bits can be colored by an operating system.

Abstract: A method for accessing an extended memory, a device, and a system are disclosed. According to the method, after receiving a first memory access requests from a processor system in a computer, an extended memory controller sends a read request for obtaining to-be-accessed data to the extended memory and return, to the processor system, a first response message indicating the to-be-accessed data has not been obtained. The extended memory controller writes the to-be-accessed data into a data buffer after receiving the to-be-accessed data returned by the extended memory. After receiving, from the processor system, a second memory access request comprising a second access address, the extended memory controller returns, to the processor system, the to-be-accessed data in the data buffer in response to the second memory access request, wherein the second access address is different from the first access address and points to the physical address of the to-be-accessed data.

Abstract: A message-based memory access apparatus and an access method thereof are disclosed, The message-based memory access apparatus includes: a message-based command bus, configured to transmit a message-based memory access instruction generated by the CPU to instruct a memory system to perform a corresponding operation; a message-based memory controller, configured to package a CPU request into a message packet and sent the packet to a storage module, and parse a message packet returned by the storage module and return data to the CPU; a message channel, configured to transmit a request message packet and a response message packet; and the storage module, including a buffer scheduler, and configured to receive the request packet from the message-based memory controller and process the corresponding request.

Abstract: A memory monitoring method and a computing system. The computing system includes a processor, a memory and a monitor. The monitor obtains memory unit access information and process information of the computer system. The memory unit access information includes the number of access times of each memory unit of the memory. The process information includes information about a mapping relationship between a virtual address and a physical address of each memory units accessed by the current running process. After generating monitoring information, which includes the frequency at which the current running process accesses each memory unit, according to the memory unit access information and the process information, the monitor feeds the monitoring information back to the processor. Thus, the processor can perform memory management according to the monitoring information.

Abstract: The present invention discloses a memory access method, a buffer scheduler, and a memory module, which can support multiple application scenarios without changing the memory module or a memory chip. The method includes: receiving an operation request message for memory access data, where the operation request message includes tag information of the memory access data, operation information of the memory access data, and a memory address of the memory access data; and performing, according to at least one of the tag information of the memory access data, a memory address of the memory access data, and the operation information of the memory access data, an operation on the tag of the memory access data and/or the memory access data stored in the memory module. The present invention is applicable to the computer field.