Abstract: Techniques for estimating runtimes of one or more machine learning tasks are provided. For example, one or more embodiments described herein can regard a system that can comprise a memory that stores computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an extraction component that can extract a parameter from a machine learning task. The parameter can define a performance characteristic of the machine learning task. Also, the computer executable components can comprise a model component that can generate a model based on the parameter. Further, the computer executable components can comprise an estimation component that can generate an estimated runtime of the machine learning task based on the model.

Abstract: Techniques for estimating runtimes of one or more machine learning tasks are provided. For example, one or more embodiments described herein can regard a system that can comprise a memory that stores computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an extraction component that can extract a parameter from a machine learning task. The parameter can define a performance characteristic of the machine learning task. Also, the computer executable components can comprise a model component that can generate a model based on the parameter. Further, the computer executable components can comprise an estimation component that can generate an estimated runtime of the machine learning task based on the model.

Abstract: Techniques for estimating runtimes of one or more machine learning tasks are provided. For example, one or more embodiments described herein can regard a system that can comprise a memory that stores computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an extraction component that can extract a parameter from a machine learning task. The parameter can define a performance characteristic of the machine learning task. Also, the computer executable components can comprise a model component that can generate a model based on the parameter. Further, the computer executable components can comprise an estimation component that can generate an estimated runtime of the machine learning task based on the model.

Abstract: A method includes a computer device receiving a branch instruction; the computer device managing two tables, where a first table relates to application blocks and a second table relates to available address slots; and the computer device calculating a target of the branch instruction using a branch-to-link register, the computer device optimizes re-wiring in a cache using the calculation and the managed two tables.

Abstract: Techniques for estimating runtimes of one or more machine learning tasks are provided. For example, one or more embodiments described herein can regard a system that can comprise a memory that stores computer executable components. The system can also comprise a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can comprise an extraction component that can extract a parameter from a machine learning task. The parameter can define a performance characteristic of the machine learning task. Also, the computer executable components can comprise a model component that can generate a model based on the parameter. Further, the computer executable components can comprise an estimation component that can generate an estimated runtime of the machine learning task based on the model.

Abstract: Software-managed resources are used to utilize effective-to-real memory address translation for synchronization among processes executing on processor cores in a multi-core computing system. A failure to find a pre-determined effective memory address translation in an effective-to-real memory address translation table on a first processor core triggers an address translation exception in a second processor core and causes an exception handler on the second processor core to start a new process, thereby acting as a means to achieve synchronization among processes on the first processor core and the second processor core. The specific functionality is implemented in the exception handler, which is tailored to respond to the exception based on the address that generated it.

Abstract: Software-managed resources are used to utilize effective-to-real memory address translation for synchronization among processes executing on processor cores in a multi-core computing system. A failure to find a pre-determined effective memory address translation in an effective-to-real memory address translation table on a first processor core triggers an address translation exception in a second processor core and causes an exception handler on the second processor core to start a new process, thereby acting as a means to achieve synchronization among processes on the first processor core and the second processor core. The specific functionality is implemented in the exception handler, which is tailored to respond to the exception based on the address that generated it.

Abstract: Software-managed resources are used to utilize effective-to-real memory address translation for synchronization among processes executing on processor cores in a multi-core computing system. A failure to find a pre-determined effective memory address translation in an effective-to-real memory address translation table on a first processor core triggers an address translation exception in a second processor core and causes an exception handler on the second processor core to start a new process, thereby acting as a means to achieve synchronization among processes on the first processor core and the second processor core. The specific functionality is implemented in the exception handler, which is tailored to respond to the exception based on the address that generated it.

Abstract: A method includes a computer device receiving a branch instruction; the computer device managing two tables, where a first table relates to application blocks and a second table relates to available address slots; and the computer device calculating a target of the branch instruction using a branch-to-link register, the computer device optimizes re-wiring in a cache using the calculation and the managed two tables.

Abstract: Software-managed resources are used to utilize effective-to-real memory address translation for synchronization among processes executing on processor cores in a multi-core computing system. A failure to find a pre-determined effective memory address translation in an effective-to-real memory address translation table on a first processor core triggers an address translation exception in a second processor core and causes an exception handler on the second processor core to start a new process, thereby acting as a means to achieve synchronization among processes on the first processor core and the second processor core. The specific functionality is implemented in the exception handler, which is tailored to respond to the exception based on the address that generated it.