Abstract: Embodiments for implementing mixed precision learning for neural networks by a processor. A neural network may be replicated into a plurality of replicated instances and each of the plurality of replicated instances differ in precision used for representing and determining parameters of the neural network. Data instances may be routed to one or more of the plurality of replicated instances for processing according to a data pre-processing operation.

Abstract: A method for transparently moving a block of memory with respect to an application using the block of memory, includes inserting, by a compiler, in an application that includes a memory allocation call, instructions for transparently moving a block of memory with respect to an application using the block of memory. The instructions include obtaining a first pointer returned by a memory allocator, where the first pointer points to an internal data structure, the internal data structure includes a read-write lock and a second pointer, and the second pointer points to an actual memory block. The instructions further include acquiring a read lock on a read-write lock in the internal data structure, before the first pointer is used by the application, obtaining the second pointer to the actual memory block, and dereferencing the second pointer to access the actual memory block for the application data.

Abstract: A method for transparently moving a block of memory with respect to an application using the block of memory, includes inserting, by a compiler, in an application that includes a memory allocation call, instructions for transparently moving a block of memory with respect to an application using the block of memory. The instructions include obtaining a first pointer returned by a memory allocator, where the first pointer points to an internal data structure, the internal data structure includes a read-write lock and a second pointer, and the second pointer points to an actual memory block. The instructions further include acquiring a read lock on a read-write lock in the internal data structure, before the first pointer is used by the application, obtaining the second pointer to the actual memory block, and dereferencing the second pointer to access the actual memory block for the application data.

Abstract: Embodiments for implementing partial synchronization between compute processes based on threshold specification in a computing environment. One or more compute processes may be synchronized in one of a plurality of types of computing platforms using a barrier having a barrier release condition based on a threshold of one or more measures. The barrier is defined according to one or more parameters. The one or more compute processes may be released via the barrier upon exceeding the threshold of the one or more measures.

Abstract: Embodiments for implementing mixed precision learning for neural networks by a processor. A neural network may be replicated into a plurality of replicated instances and each of the plurality of replicated instances differ in precision used for representing and determining parameters of the neural network. Data instances may be routed to one or more of the plurality of replicated instances for processing according to a data pre-processing operation.

Abstract: Embodiments for implementing partial synchronization between compute processes based on threshold specification in a computing environment. One or more compute processes may be synchronized in one of a plurality of types of computing platforms using a barrier having a barrier release condition based on a threshold of one or more measures. The barrier is defined according to one or more parameters. The one or more compute processes may be released via the barrier upon exceeding the threshold of the one or more measures.

Abstract: According to one embodiment of the present invention, a computer system is provided where the computer system includes a main processor, first and second active memory device. The computer system is configured to perform a method including receiving an executable module generated by a compiler, wherein the executable module includes a code section identified as executable by a first processing element in the first active memory device and a second processing element in the second active memory device. The method includes copying the code section to memory in the first device based on the code section being executable on the first device, copying the code section from the first active memory device to an instruction buffer of the first processing element and copying the code section from the first device to the second device based on the code section being executable on the second device.

Abstract: According to one embodiment, a method for a compiler to produce an executable module to be executed by a computer system including a main processor and active memory devices includes dividing source code into code sections, identifying a first code section to be executed by the active memory devices, wherein the first code section is one of the code sections and identifying data structures that are used by the first code section. The method also includes classifying the data structures based on pre-defined attributes, formulating, by the compiler, a storage mapping plan for the data structures based on the classifying and generating, by the compiler, mapping code that implements the storage mapping plan, wherein the mapping code is part of the executable module and wherein the mapping code maps storing of the data structures to storage locations in the active memory devices.

Abstract: According to one embodiment, a system including a compiler to produce an executable module to be executed by a computer system including a main processor and active memory devices is provided. The system configured to perform a method including dividing source code into code sections, identifying a first code section to be executed by the active memory devices and identifying data structures that are used by the first code section. The method also includes classifying the data structures based on pre-defined attributes, formulating, by the compiler, a storage mapping plan for the data structures based on the classifying and generating, by the compiler, mapping code that implements the storage mapping plan, wherein the mapping code is part of the executable module and wherein the mapping code maps storing of the data structures to storage locations in the active memory devices.

Abstract: According to one embodiment of the present invention, a method for operation of a computer system including a main processor, a first and a second active memory device includes receiving an executable module generated by a compiler, wherein the executable module includes a code section identified as executable by a first processing element in the first active memory device and a second processing element in the second active memory device. The method further includes copying the code section to memory in the first device based on the code section being executable on the first device, copying the code section from the memory in the first active memory device to an instruction buffer of the first processing element and copying the code section from the memory in the first device to the second device based on the code section being executable on the second device.

Abstract: According to one embodiment, a method for a compiler to produce an executable module to be executed by a computer system including a main processor and active memory devices includes dividing source code into code sections, identifying a first code section to be executed by the active memory devices, wherein the first code section is one of the code sections and identifying data structures that are used by the first code section. The method also includes classifying the data structures based on pre-defined attributes, formulating, by the compiler, a storage mapping plan for the data structures based on the classifying and generating, by the compiler, mapping code that implements the storage mapping plan, wherein the mapping code is part of the executable module and wherein the mapping code maps storing of the data structures to storage locations in the active memory devices.

Abstract: According to one embodiment of the present invention, a computer system is provided where the computer system includes a main processor, first and second active memory device. The computer system is configured to perform a method including receiving an executable module generated by a compiler, wherein the executable module includes a code section identified as executable by a first processing element in the first active memory device and a second processing element in the second active memory device. The method includes copying the code section to memory in the first device based on the code section being executable on the first device, copying the code section from the first active memory device to an instruction buffer of the first processing element and copying the code section from the first device to the second device based on the code section being executable on the second device.

Abstract: According to one embodiment of the present invention, a method for operation of a computer system including a main processor, a first and a second active memory device includes receiving an executable module generated by a compiler, wherein the executable module includes a code section identified as executable by a first processing element in the first active memory device and a second processing element in the second active memory device. The method further includes copying the code section to memory in the first device based on the code section being executable on the first device, copying the code section from the memory in the first active memory device to an instruction buffer of the first processing element and copying the code section from the memory in the first device to the second device based on the code section being executable on the second device.

Abstract: Target memory hierarchy specification in a multi-core computer processing system is provided including a system for implementing prefetch instructions. The system includes a first core processor, a dedicated cache corresponding to the first core processor, and a second core processor. The second core processor includes instructions for executing a prefetch instruction that specifies a memory location and the dedicated local cache corresponding to the first core processor. Executing the prefetch instruction includes retrieving data from the memory location and storing the retrieved data on the dedicated local cache corresponding to the first core processor.

Abstract: One embodiment of the present method and apparatus for application-specific dynamic cache placement includes grouping sets of data in a cache memory system into two or more virtual partitions and processing a load/store instruction in accordance with the virtual partitions, where the load/store instruction specifies at least one of the virtual partitions to which the load/store instruction is assigned.

Abstract: One embodiment of the present method and apparatus for dynamic priority-based cache replacement includes selectively assigning relative priority values to at least a subset of data items in the cache memory system, fetching a new data item to load into the cache memory system, the data item being associated with a priority value, and selecting an existing data item from the cache memory system to replace with the new data item, in accordance with the relative priority values and the priority value of the new data item.

Abstract: One embodiment of the present method and apparatus for application-specific dynamic cache placement includes grouping sets of data in a cache memory system into two or more virtual partitions and processing a load/store instruction in accordance with the virtual partitions, where the load/store instruction specifies at least one of the virtual partitions to which the load/store instruction is assigned.

Abstract: One embodiment of the present method and apparatus for application-specific dynamic cache placement includes grouping sets of data in a cache memory system into two or more virtual partitions and processing a load/store instruction in accordance with the virtual partitions, where the load/store instruction specifies at least one of the virtual partitions to which the load/store instruction is assigned.

Abstract: One embodiment of the present method and apparatus for dynamic priority-based cache replacement includes selectively assigning relative priority values to at least a subset of data items in the cache memory system, fetching a new data item to load into the cache memory system, the data item being associated with a priority value, and selecting an existing data item from the cache memory system to replace with the new data item, in accordance with the relative priority values and the-priority value of the new data item.

Abstract: A compiler implemented software cache apparatus and method in which non-aliased explicitly fetched data are excluded are provided. With the mechanisms of the illustrative embodiments, a compiler uses a forward data flow analysis to prove that there is no alias between the cached data and explicitly fetched data. Explicitly fetched data that has no alias in the cached data are excluded from the software cache. Explicitly fetched data that has aliases in the cached data are allowed to be stored in the software cache. In this way, there is no runtime overhead to maintain the correctness of the two copies of data. Moreover, the number of lines of the software cache that must be protected from eviction is decreased. This leads to a decrease in the amount of computation cycles required by the cache miss handler when evicting cache lines during cache miss handling.