Abstract: A microcontroller measures capacitance of capacitive sensors having guard rings associated therewith. A guard ring is provided around each capacitive sensor plate and is charged to substantially the same voltage as a voltage on the associated capacitive sensor plate. The guard ring reduces parasitic capacitances of the capacitive sensor plate caused by differences in voltage potentials between the capacitive sensor plate, and adjacent circuit conductors, ground planes and power planes. An analog output is buffered and coupled to an analog input coupled to the capacitive sensor plate, and is used to drive the guard ring voltage to substantially the same voltage as the voltage on the capacitive sensor plate.

Abstract: An apparatus for selecting a plurality of input signals from a plurality of y signals in a device has a switching matrix with a plurality of n to 1 mulitplexers, wherein each n to 1 multiplexer is assigned to a different input set of n of the y signals wherein a subset of less than n input signals of each set of input signals of each of the n to 1 multiplexers is also a subset of input signals of another n to 1 multiplexer.

Abstract: A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. The slope control unit comprises a capacitor coupled between an input and an output of the slope control unit, a switch for discharging the capacitor and a constant current source for charging the capacitor. Slope compensation parameters may be changed during operation with a programmable constant current source. The slope compensation module may also function as an analog sawtooth waveform frequency generator, and as an analog pulse width modulation (PWM) generator. Charging the capacitor generates a linearly decreasing (negative slope) ramp voltage for modulating a feedback error voltage into a slope compensated feedback error voltage. Capacitor charging may be controlled from a pulse width modulation signal. Opening of the switch may be programmably delayed, and a minimum closed time thereof may also be programmed during operation of the slope compensation module.

Abstract: A complementary output generator (COG) module generates at least two complementary outputs determined by rising and falling event sources. In a simple configuration of the COG module, the rising and falling event sources are the same signal which is a signal having the desired period and duty cycle. The COG module converts this single signal input into dual complementary outputs. The frequency and duty cycle of the dual outputs substantially match those of the single input signal. Blanking and deadband times may be introduced between the complementary outputs, and the dual complementary outputs may also be phase delayed. In addition the COG module may provide up to four outputs for controlling half and full-wave bridge power applications.

Abstract: A guard ring is provided around each capacitive sensor plate and charged to substantially the same voltage as a voltage on the capacitive sensor plate. The guard ring reduces parasitic capacitances of the capacitive sensor plate caused by differences in voltage potentials between the capacitive sensor plate, and adjacent circuit conductors, ground planes and power planes. Two digital outputs and associated voltage divider resistors are used to drive the guard ring voltage to substantially the same voltage as the voltage on the capacitive sensor plate.

Abstract: An analog-to-digital (ADC) controller is used in combination with a digital processor of a microcontroller to control the operation of capacitance measurements using the capacitive voltage division (CVD) method. The ADC controller handles the CVD measurement process instead of the digital processor having to run additional program steps for controlling charging and discharging of a capacitive touch sensor and sample and hold capacitor, then coupling these two capacitors together, and measuring the resulting voltage charge thereon in determining the capacitance thereof. The ADC controller may be programmable and its programmable parameters stored in registers.

Abstract: A microprocessor or microcontroller device may have a central processing unit (CPU), a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks, wherein a bank select register determines which memory bank is currently coupled with the CPU. Furthermore, a first and second set of special function registers are provided, wherein upon occurrence of a context switch either the first or the second set of special function register are selected as active context registers for the CPU and the respective other set of special function registers are selected as inactive context registers, wherein at least some of the registers of the active context registers are memory mapped to more than two memory banks of the data memory and wherein all registers of the inactive context registers are memory mapped to at least one memory location within the data memory.

Abstract: An automated sequencer for a microcontroller is provided which makes a CVD conversion process a hardware function. The sequencer controls the charging/discharging of the sensor and ADC sample-and-hold capacitances, as well as the voltage division process. It also initiates the ADC conversion, with an optional second conversion for greater resolution, or a differential conversion.

Abstract: An ADC module includes an analog to digital converter coupled with an analog bus, wherein the an analog to digital converter comprises a main sample and hold capacitor; and a plurality of additional sample and hold capacitances which can be programmably coupled in parallel with said main sample and hold capacitance.

Abstract: A complementary output generator (COG) module generates at least two complementary outputs determined by rising and falling event sources. In a simple configuration of the COG module, the rising and falling event sources are the same signal which is a signal having the desired period and duty cycle. The COG module converts this single signal input into dual complementary outputs. The frequency and duty cycle of the dual outputs substantially match those of the single input signal. Blanking and deadband times may be introduced between the complementary outputs, and the dual complementary outputs may also be phase delayed. In addition the COG module may provide up to four outputs for controlling half and full-wave bridge power applications.

Abstract: A slope compensation module provides slope compensation of a switched-mode power supply using current mode control. The slope control unit comprises a capacitor coupled between an input and an output of the slope control unit, a switch for discharging the capacitor and a constant current source for charging the capacitor. Slope compensation parameters may be changed during operation with a programmable constant current source. The slope compensation module may also function as an analog sawtooth waveform frequency generator, and as an analog pulse width modulation (PWM) generator. Charging the capacitor generates a linearly decreasing (negative slope) ramp voltage for modulating a feedback error voltage into a slope compensated feedback error voltage. Capacitor charging may be controlled from a pulse width modulation signal. Opening of the switch may be programmably delayed, and a minimum closed time thereof may also be programmed during operation of the slope compensation module.

Abstract: A processor includes a RISC CPU core; and a plurality of peripherals including one or more configurable logic cell peripherals. The configurable logic cell peripheral may be configured to allow real-time software access to internal configuration and signals paths of the processor. The configurable logic cell peripheral may have real-time configuration control.

Abstract: A microprocessor or microcontroller device may have a central processing unit (CPU), a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks, wherein a bank select register determines which memory bank is currently coupled with the CPU. Furthermore, a first and second set of special function registers are provided, wherein upon occurrence of a context switch either the first or the second set of special function register are selected as active context registers for the CPU and the respective other set of special function registers are selected as inactive context registers, wherein at least some of the registers of the active context registers are memory mapped to more than two memory banks of the data memory and wherein all registers of the inactive context registers are memory mapped to at least one memory location within the data memory.

Abstract: A processor includes a RISC CPU core and a plurality of peripherals including a configurable logic cell peripheral. The configurable logic cell peripheral may be configured to combine a plurality of inputs into a single output. The configurable logic cell may be programmable to function as one of a plurality of predetermined logic functions.

Abstract: A processor includes a RISC CPU core; and a plurality of peripherals including one or more configurable logic cell peripherals. The configurable logic cell peripheral may be configured to allow real-time software access to internal configuration and signals paths of the processor. The configurable logic cell peripheral may have real-time configuration control.

Abstract: An integrated circuit device, in accordance with embodiments as claimed includes a central processing core; and a plurality of peripherals operably coupled to the RISC CPU core. In some embodiments, the plurality of peripherals include at least one configurable logic cell peripheral having more inputs than input-output connections on the integrated circuit device. In some embodiments, the inputs include one or more inputs from one or more integrated circuit subsystems.

Abstract: An apparatus for selecting a plurality of input signals from a plurality of y signals in a device has a switching matrix with a plurality of n to 1 mulitplexers, wherein each n to 1 multiplexer is assigned to a different input set of n of the y signals wherein a subset of less than n input signals of each set of input signals of each of the n to 1 multiplexers is also a subset of input signals of another n to 1 multiplexer.