Abstract: Techniques are disclosed relating to graphics processor data caches. In some embodiments, datapath executes instructions that operate on input operands from architectural registers. Data cache circuitry caches architectural register data for the datapath circuitry. Scoreboard circuitry tracks, for a given architectural register: map information that indicates whether the architectural register is mapped to an entry of the data cache circuitry and a pointer to the entry of the data cache circuitry. Tiered scoreboard circuitry and data storage circuitry may be implemented (e.g., to provide fast scoreboard access for active threads and to give a landing spot for long-latency data retrieval operations). Various disclosed techniques may improve cache performance, reduce power consumption, reduce area, or some combination thereof.

Abstract: Techniques are disclosed relating to eviction control for cache lines that store register data. In some embodiments, memory hierarchy circuitry is configured to provide memory backing for register operand data in one or more cache circuits. Lock circuitry may control a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated, by decode circuitry, as being utilized by decoded instructions of the first thread. The lock circuitry may preserve register operand data in the one or more cache circuits, including to prevent eviction of a given cache line from a cache circuit based on an asserted lock indicator. The lock circuitry may clear the first set of lock indicators in response to a reset event. Disclosed techniques may advantageously retain relevant register information in the cache with limited control circuit area.

Abstract: Techniques are disclosed relating to eviction control for cache lines that store register data. In some embodiments, memory hierarchy circuitry is configured to provide memory backing for register operand data in one or more cache circuits. Lock circuitry may control a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated, by decode circuitry, as being utilized by decoded instructions of the first thread. The lock circuitry may preserve register operand data in the one or more cache circuits, including to prevent eviction of a given cache line from a cache circuit based on an asserted lock indicator. The lock circuitry may clear the first set of lock indicators in response to a reset event. Disclosed techniques may advantageously retain relevant register information in the cache with limited control circuit area.

Abstract: Techniques are disclosed relating to eviction control for cache lines that store register data. In some embodiments, memory hierarchy circuitry is configured to provide memory backing for register operand data in one or more cache circuits. Lock circuitry may control a first set of lock indicators for a set of registers for a first thread, including to assert one or more lock indicators for registers that are indicated, by decode circuitry, as being utilized by decoded instructions of the first thread. The lock circuitry may preserve register operand data in the one or more cache circuits, including to prevent eviction of a given cache line from a cache circuit based on an asserted lock indicator. The lock circuitry may clear the first set of lock indicators in response to a reset event. Disclosed techniques may advantageously retain relevant register information in the cache with limited control circuit area.

Abstract: Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

Abstract: The present invention discloses an optimization method for a screen surface dynamic load of a vibrating screen. The method includes the following steps: step 1. selecting design variables, and establishing an experimental matrix; step 2. performing a response curved surface experiment; step 3. establishing two double-objective optimization models and solving the same to obtain two groups of Pareto solution sets, wherein the solution sets respectively represent screening efficiency optimization paths of the vibrating screen under the conditions of a high screen surface dynamic load and a low screen surface dynamic load; and step 4. calculating an optimization space for a screen surface dynamic load under a high screening efficiency. According to the method of the present invention, the screen surface dynamic load can be directly reduced, and the service life of the screen surface and the whole vibrating screen is prolonged.

Abstract: The present invention discloses an optimization method for a screen surface dynamic load of a vibrating screen. The method includes the following steps: step 1. selecting design variables, and establishing an experimental matrix; step 2. performing a response curved surface experiment; step 3. establishing two double-objective optimization models and solving the same to obtain two groups of Pareto solution sets, wherein the solution sets respectively represent screening efficiency optimization paths of the vibrating screen under the conditions of a high screen surface dynamic load and a low screen surface dynamic load; and step 4. calculating an optimization space for a screen surface dynamic load under a high screening efficiency. According to the method of the present invention, the screen surface dynamic load can be directly reduced, and the service life of the screen surface and the whole vibrating screen is prolonged.

Abstract: Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

Abstract: Techniques are disclosed relating to arbitration for computer memory resources. In some embodiments, an apparatus includes queue circuitry that implements multiple queues configured to queue requests to access a memory bus. Control circuitry may, in response to detecting a first threshold condition associated with the queue circuitry, generate a first snapshot that indicates numbers of requests in respective queues of the multiple queues at a first time. The control circuitry may generate a second snapshot that indicates numbers of requests in respective queues of the multiple queues at a second time that is subsequent to the first time. The control circuitry may arbitrate between requests from the multiple queues to select requests to access the memory bus, where the arbitration is based on snapshots to which requests from the multiple queues belong. Disclosed techniques may approximate age-based scheduling while reducing area and power consumption.

Abstract: Embodiments discussed herein facilitate determination of risk of relapse of AML post-transplant. One example embodiment is a method, comprising: accessing a digital whole slide image (WSI) comprising a post-transplant bone marrow aspirate from a patient that has acute myeloid leukemia (AML); segmenting one or more myeloblasts on the digital WSI; extracting one or more features from the segmented one or more myeloblasts; providing the one or more features extracted from the segmented one or more myeloblasts to a trained machine learning model; and receiving, from the trained machine learning model, an indication of a risk of relapse of the AML.

Abstract: A collapsible wheeled walker with two side frames and two height adjustable upper body supports. The apparatus includes a plurality of wheel direction locks each coupled to a wheel and adapted to lock the wheel in fixed moving direction or to release the wheel to turn freely. The apparatus may include a seat that is slidably attached to the two side frames and is movable between a front position for walking inside the frames and a rear position sitting. The apparatus may be converted to a transport chair by locking front wheel and releasing the rear wheels, and sliding the movable seat to the rear position. It may include an X-folder that facilitates collapsing the walker to a small footprint. It may also include two forearm gutters as part of the upper body supports that give the user an upright walking posture for health benefits.

Abstract: A collapsible wheeled walker with two side frames and two height adjustable upper body supports. The apparatus includes a seat that is slidably attached to the two side frames and is movable between a front position to facilitate an ample walking space inside the frames and a rear position for a user to sit. The apparatus may include an X-folder that facilitates collapsing the walker to a small footprint for storage and transportation. It may also include a left forearm gutter and a right forearm gutter as part of the upper body supports that give the user an upright walking posture for health benefits.

Abstract: A collapsible wheeled walker with two side frames and two height adjustable upper body supports. The apparatus includes a seat that is slidably attached to the two side frames and is movable between a front position to facilitate an ample walking space inside the frames and a rear position for a user to sit. The apparatus may include an X-folder that facilitates collapsing the walker to a small footprint for storage and transportation. It may also include a left forearm gutter and a right forearm gutter as part of the upper body supports that give the user an upright walking posture for health benefits.

Abstract: A collapsible wheeled walker with two side frames and two height adjustable upper body supports. The apparatus includes a seat that is slidably attached to the two side frames and is movable between a front position to facilitate an ample walking space inside the frames and a rear position for a user to sit. The apparatus may include an X-folder that facilitates collapsing the walker to a small footprint for storage and transportation. It may also include a left forearm gutter and a right forearm gutter as part of the upper body supports that give the user an upright walking posture for health benefits.

Abstract: A collapsible wheeled walker with two side frames and two height adjustable upper body supports. The apparatus includes a seat that is slidably attached to the two side frames and is movable between a front position to facilitate an ample walking space inside the frames and a rear position for a user to sit. The apparatus may include an X-folder that facilitates collapsing the walker to a small footprint for storage and transportation. It may also include a left forearm gutter and a right forearm gutter as part of the upper body supports that give the user an upright walking posture for health benefits.

Abstract: A collapsible Wheeled Walker with two side frames and two height adjustable upper body supports. The apparatus includes a plurality of wheel direction locks each coupled to a wheel and adapted to lock the wheel in fixed moving direction or to release the wheel to turn freely. The apparatus may include a seat that is slidably attached to the two side frames and is movable between a front position for walking inside the frames and a rear position sitting. The apparatus may be converted to a transport chair by locking front wheel and releasing the rear wheels, and sliding the movable seat to the rear position. It may include an X-folder that facilitates collapsing the Walker to a small footprint. It may also include two forearm gutters as part of the upper body supports that give the user an upright walking posture for health benefits.