Abstract: A nonvolatile storage device includes a power management system with a power loss imminent (PLI) capacitor to provide backup energy in case system power is lost. The power management system includes a circuit with a charging path for the PLI capacitor that includes a series current-limiting circuit, and a diode coupled in parallel with the current-limiting circuit, the diode having a cathode coupled to the charging circuit and an anode to couple to the PLI capacitor.

Abstract: Systems, apparatuses and methods may provide for technology that applies a constant current to a capacitor, wherein the constant current causes a linear voltage increase in the capacitor, and determines a capacitance based on the constant current, a voltage change in the capacitor during the linear voltage increase, and a time change corresponding to the voltage change.

Abstract: In embodiments, an apparatus includes a burst current monitor, to detect a burst of input current drawn by a SSD from a host above a pre-defined burst threshold, and control logic coupled to the burst current monitor. The control logic, in response to the detection by the burst current monitor of the input current above the burst threshold, causes a capacitor of the SSD to supply an assistance current to the SSD, to reduce the input current drawn by the SSD. In embodiments, the capacitor is a hold-up capacitor disposed in a PLI circuit of the SSD, and the apparatus is integrated within a hold-up control logic sub-circuit of the PLI circuit.

Abstract: An apparatus is described. The apparatus includes a power management integrated circuit (PMIC) semiconductor chip having logic circuitry to implement a PMIC/PMIC interface having a downstream signal line and an upstream signal line. The downstream signal line to communicate any of multiple states that a downstream PMIC semiconductor chip is to implement with one of multiple voltage levels, where, different ones of the multiple voltage levels correspond to different ones of the multiple states. The upstream signal line is to communicate whether or not the downstream PMIC semiconductor chip is ready to receive a next one of the multiple voltage levels.

Abstract: An apparatus is described. The apparatus includes a power management integrated circuit (PMIC) semiconductor chip having logic circuitry to implement a PMIC/PMIC interface having a downstream signal line and an upstream signal line. The downstream signal line to communicate any of multiple states that a downstream PMIC semiconductor chip is to implement with one of multiple voltage levels, where, different ones of the multiple voltage levels correspond to different ones of the multiple states. The upstream signal line is to communicate whether or not the downstream PMIC semiconductor chip is ready to receive a next one of the multiple voltage levels.

Abstract: In embodiments, an apparatus includes a burst current monitor, to detect a burst of input current drawn by a SSD from a host above a pre-defined burst threshold, and control logic coupled to the burst current monitor. The control logic, in response to the detection by the burst current monitor of the input current above the burst threshold, causes a capacitor of the SSD to supply an assistance current to the SSD, to reduce the input current drawn by the SSD. In embodiments, the capacitor is a hold-up capacitor disposed in a PLI circuit of the SSD, and the apparatus is integrated within a hold-up control logic sub-circuit of the PLI circuit.

Abstract: A nonvolatile storage device includes a power management system with a power loss imminent (PLI) capacitor to provide backup energy in case system power is lost. The power management system includes a circuit with a charging path for the PLI capacitor that includes a series current-limiting circuit, and a diode coupled in parallel with the current-limiting circuit, the diode having a cathode coupled to the charging circuit and an anode to couple to the PLI capacitor.

Abstract: Provided is a memory device, comprising a non-volatile memory, an energy store coupled to the non-volatile memory, and a power management module configurable to power up the non-volatile memory and provide read access to the non-volatile memory, in response to the energy store being charged to at least a first predetermined level. Provided also is a computational device that includes the memory device. Provided also is a method in which an energy store coupled to a non-volatile memory of a memory device is charged to at least a first predetermined level. The non-volatile memory is powered up and read access is provided to the non-volatile memory, in response to charging the energy store to at least the first predetermined level.

Abstract: Provided is a memory device, comprising a non-volatile memory, an energy store coupled to an input power module of the non-volatile memory, and a power management module configurable to determine whether or not to supply backup power to the non-volatile memory via the energy store to initiate a shutdown process, based on differentiating a voltage glitch from an actual loss of power in a power line. Provided also is a computational device that includes the memory device. Provided also is a method in which a power management module of the memory device determines whether or not to supply backup power to the non-volatile memory via the energy store to initiate a shutdown process, based on differentiating a voltage glitch from an actual loss of power in a power line.

Abstract: Provided is a memory device, comprising a non-volatile memory, an energy store coupled to an input power module of the non-volatile memory, and a power management module configurable to determine whether or not to supply backup power to the non-volatile memory via the energy store to initiate a shutdown process, based on differentiating a voltage glitch from an actual loss of power in a power line. Provided also is a computational device that includes the memory device. Provided also is a method in which a power management module of the memory device determines whether or not to supply backup power to the non-volatile memory via the energy store to initiate a shutdown process, based on differentiating a voltage glitch from an actual loss of power in a power line.

Abstract: Herein are disclosed optoelectronic methods and devices for detecting the presence of an analyte. Such methods and devices may comprise at least one sensing element that is responsive to the presence of an analyte of interest and that may be interrogated optically by the use of at least one light source and at least one light detector.

Abstract: Herein are disclosed optoelectronic methods and devices for detecting the presence of an analyte. Such methods and devices may comprise at least one sensing element that is responsive to the presence of an analyte of interest and that may be interrogated optically by the use of at least one light source and at least one light detector.

Abstract: Herein are disclosed optoelectronic methods and devices for detecting the presence of an analyte. Such methods and devices may comprise at least one sensing element that is responsive to the presence of an analyte of interest and that may be interrogated optically by the use of at least one light source and at least one light detector.

Abstract: Herein are disclosed optoelectronic methods and devices for detecting the presence of an analyte. Such methods and devices may comprise at least one sensing element that is responsive to the presence of an analyte of interest and that may be interrogated optically by the use of at least one light source and at least one light detector.